CRU Weekly meeting (18 January 2017)
Present: Alex, Erno, PiPPo, Sanjoy, Tivada, Shuaib, mazsi
Secretary: Erno(13), PiPPo(9), Shuaib(1), mazsi(9)
Actions:
- step-by-step test instructions (Test scripts): send first version to mazsi by monday.
- new time slot for CRU weekly meeting: answer doodle poll posted by Erno.
- SMA cables for the lab to be ordered.
- external jitter cleaner PLL devkit to be ordered.
Report on Actions:
- PiPPo - 2nd test machine for our 2nd Altera A10 GX devkit is on it's way.
1. 10G PON
- mazsi - not much progress, working on PON RX -> GBT TX clock domain crossing.
2. GBT
- Erno - Working on the automated GBT test scripts.
- Erno - took quick look on GBT 5.0.0 release changelog: we are not affected by the bugs fixed (we use our own gearbox).
no trace of 240 MHz version in the the release - will contact them and check.
3. DCS
- Sanjoy - i2c slave scan script done. working on C code, which generates TCL script, which configures external PLL.
- PiPPo - rewrote GBT IC modules - no timing error. got GBT EC module from stephan / TPC. some polishing to do, will post new version in GIT for integration.
- Pascal - did the DCS interfacing: DCS can do BAR read/write. no register name to register address mapping in our code, so DCS passes raw register address -> we will need to publish interworking document (which describes registers).
4. PCIe
- project compiled with 16.1
5. Integration
AOB
- Tivadar - production: there were part number mismatches in documentation, production was stopped for a week, later resumed. 4 PCBs are available (from sanmina), 1 will be populated for now (possibly in ~1 week), if all tests are fine a 2nd PCB will also be populated (~3 days work). board bringup will start in india (test FW needed in ~2 weeks). another 4 PCBs from another company: was not successful.
- PiPPo - frontend tests: TPC taking data (link errors were due to power supply error), MCH: reading out data, MID: some problems (probably because of old version of GBT on FEC), FIT: still not decided on GBT uplink data format (packetized or continuous stream).
- Ongoing discussions about the modified PCIe40 clock tree (different PLL, reference clock modifications)
Travels/Vacations
- Tivadar: will travell to CERN on Jan 23.
- Jean-Pierre Cachemiche: will be at CERN next week.
- Joe Schambach (ITS): at CERN possibly from Jan 23.
- Jan 26.: national holiday in india.
- March 1.: Sanjoy travels to CERN (tentative).
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