| ATLAS Slides | |
| Report number | ATL-PHYS-SLIDE-2017-041 |
| Title | Performance and description of the upgraded readout with the new back-end electronics for the ATLAS Pixel detector |
| Author(s) | Yajima, Kazuki (Osaka University) |
| Corporate author(s) | The ATLAS collaboration |
| Collaboration | ATLAS Collaboration |
| Submitted to | 129th LHCC Meeting, CERN, Geneva, Switzerland, 22 - 23 Feb 2017 |
| Submitted by | kazuki.yajima@cern.ch on 20 Feb 2017 |
| Subject category | Particle Physics - Experiment |
| Accelerator/Facility, Experiment | CERN LHC ; ATLAS |
| Free keywords | Pixel ; IBL ; DAQ ; Upgrade ; TRACKING |
| Abstract | LHC increased drastically its performance during the RUN2 data taking, starting from a peak instantaneous luminosity of up to $5\times10^{33} \mathrm{cm}^{-2} \mathrm{s}^{-1}$ in 2015 to conclude with the record value of $1.4\times10^{34} \mathrm{cm}^{-2} \mathrm{s}^{-1}$ in November 2016. The concurrent increase of the trigger rate and event size forced the ATLAS experiment to exploit its sub-detectors to the maximum, approaching and possibly overcoming the design parameters. The ATLAS Pixel data acquisition system was upgraded to avoid possible bandwidth limitations. Two upgrades of the read-out electronics have been done. The first one during 2015/16 YETS, when the outermost pixel layer (Layer-2) was upgraded and its bandwidth was doubled. This upgrade partly contributed to maintain the data taking efficiency of the Pixel detector at a relatively high level ($\sim$99%) during the 2016 run. A similar upgrade of the read-out system for the middle layer (Layer-1) is ongoing during 2016/17 EYETS. The details of the Pixel DAQ upgrades, the performance of the Layer-2 during the 2016 run and the status of the Layer-1 upgrade are presented in this poster. |
Record created 2017-02-20, last modified 2017-02-20
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