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Description
This works presents the design and experimental study of a radiation hardened Phase Locked Loop (PLL) for high speed serial-communication links. These research results are used for the LpGBT (Low Power Gigabit Transceiver) chip which will be widely used for optical data-links between the detectors and the counting rooms in the HL–LHC experiments. The PLL features a novel LC-oscillator architecture which is 600× less sensitive than traditional structures. Additionally, the circuit uses triple-modular redundancy and is designed in 65nm CMOS. The paper will present experimental results on X-ray Total Ionizing Dose (TID), heavy ion SEU and two-photon absorption laser tests.
Summary
Future upgrades to the HL-LHC at CERN will demand ever increasing data-rates from the detector modules to the counting rooms without an increase of the overall power consumption of the links. The LpGBT (Low Power Gigabit Transceiver), which is currently being developed, will make this speed available to the experiments with an uplink data-rate of 10.24 Gbps and a downlink data-rate of 2.56 Gbps which will be widely used in the different experiments around the LHC like ATLAS, ALICE, CMS and LHCb. This work presents the design of a radiation hardened Phase Locked Loop (PLL) that will be incorporated in the PLL/CDR of the LpGBT. To ensure the stability of the link, a small single-event upset (SEU) cross section is required and a Total Ionizing Dose (TID) resistance of 200 Mrad is targeted for the overall SoC.
The PLL presented in this work has a nominal output frequency of 2.56 GHz which is locked to the 40 MHz LHC reference clock through a divide-by-64 circuit. The oscillator consists of an integrated LC-tank with MOSCAP tuning diodes which are AC-coupled to the tank to improve the SEU rejection. The LC-oscillator has a tuning range from 2.2 GHz up to 3.2 GHz. The novel tuning strategy improves the SEU sensitivity by more than 600 × compared to the standard LC tuning topology which makes this oscillator the best among current reported state-of-the-art oscillators in ionizing environments. The PLL measured jitter is less than 350 fs rms with a power consumption smaller than 10 mW at 1.2V. The radiation hardness is assured with the novel VCO architecture and the triplication of all digital blocks which use a custom digital library with enclosed-layout transistors cells for TID hardness. The phase-frequency detector in the PLL is triplicated with a novel asynchronous TMR structure such that no cycle slips can occur due to a single SEU error. A comparison in terms of SEU sensitivity is made with a non-triplicated phase-frequency detector. A detailed discussion on the charge injection mechanisms in this oscillator shows that a trade-off is required between the VCO cross section and the phase-noise (jitter)/power consumption of the oscillator together with the phase jump magnitudes encountered in the circuit. The VCO has a configurable power supply circuit which can be switched from voltage limited operation to current limited operation.
An experimental test chip has been fabricated in a 65 nm CMOS technology and measured with ionizing radiation. The experimental tests were done in a cyclotron that produces heavy ions from 3.3 up to 62.5 MeV cm²/mg and the findings were further investigated by scanning the circuit with two-photon absorption laser. X-ray TID tests up to 600 Mrad are discussed which show almost no change in the oscillation frequency since, for this topology, the frequency is essentially set by the passive LC resonant tank. Temperature effects are briefly discussed. In this paper, the design of radiation hardened PLLs for harsh environments will be discussed which is applicable to all CMOS integrated clock generation circuits.
