Speaker
Description
Monolithic Active Pixel Sensors are becoming increasingly attractive for the next generation High Energy Physics experiments. For this reason several R&D are ongoing in different laboratories to improve the performance of conventional MAPS.
In this context we present a flexible readout electronics specifically developed for the detailed characterization of MAPS. The prototype ASIC has been fabricated in 0.11 $\mu m$ CMOS technology with a die area of 2 $\times$ 2 mm$^2$ and a low voltage operation of 1.2 V.
In the presentation, the front-end electronics will be described and detailed tests obtained on a first submission will be presented.
Summary
The next generation High Energy Physics experiments requires the development of novel radiation silicon sensor technologies adequate to cover large areas. In this context, Monolithic Active Pixel Sensors (MAPS) are becoming increasingly attractive thanks to their properties such as low material budget, high granularity and the much lower cost if compared with hybrid pixel sensors. Several R&D are ongoing in different laboratories to improve the characteristics of conventional MAPS. In particular, achieving a charge collection speed as fast as possible is key to improve the sensor radiation tolerance.
Technologies that allow simultaneous integration of analog and digital electronics in the same pixel are also increasingly exploited.
In the course of an R&D project it is important to compare different sensor designs and different starting materials. In this context we have developed a flexible readout electronics that allows the detailed characterization of MAPS. A prototype ASIC has been fabricated in 0.11 μm CMOS VLSI technology with a die area of 2 x 2 mm^2 and a low voltage operation of 1.2 V. The test chip consists of a matrix of 24 X 24 pixel units organized in 4 independent sectors and an End of Column logic. Each sector consist of 6 columns of 24 pixels and can be used to test different sensor flavors. Both NMOS and PMOS can be used simultaneously.
The analogue readout is based on a Charge Sensitive Amplifier (CSA) with a feedback transistor for the reset operation, two local memories implemented by using MIM capacitors to optimize the pixel size and four buffers used to send the analogue data off-chip through dedicated data transmission lines. The preamplifier is connected to the sensing node by DC coupling. The digital logic in-pixel allows some features like internal pulse generation, baseline regulation and mask channel operation. Thanks to the baseline regulation and to the wide dynamic range of the buffers, the readout supports signals in
excess of 24 ke- . The use of a CSA makes the readout fairly insensitive to the sensor capacitance.
An additional large digital buffer, controlled by a dedicated signal have been also implemented to inject substrate noise with the aim of studying the possible noise coupling between the digital and the analogue electronics. The four sub-matrices are readout in parallel in less than 40 us with a maximum measured drop voltage of 0.7 μV. when a clock of 5 MHz is used. For each sector both the baseline and signal are sent off-chip. The design supports snapshot shutter operation with integration times as short as 100 ns and Correlated Double Sampling (CDS) to subtract offsets in common between baseline and signal and to suppress the switching noise. In the present implementation the in-pixel electronics occupies an area of 30 μm X 30 μm and, including the sensor, it allows the implementation of pixels with a total are of 40 μm X 40 μm or larger.
In the presentation, the front-end electronics will be described and detailed tests obtained on a first submission will be presented.
