With the High-Luminosity (HL) LHC ahead, bringing the discrimination power of jet-substructure-based jet tagging algorithms to Level 1 trigger selection will be a major asset to guarantee an optimal usage of the limited trigger resources at downstream steps. To do so, the CMS experiment is intensively investigating the possibility of running the particle-flow (PF) reconstruction algorithm on low-latency FPGA cards, part of the L1 hardware electronics, taking advantage of the advent of track reconstruction at L1. The availability of particle candidates at L1 opens the possibility to compute jet substructure observables and develop new boosted jet tagging algorithms to improve trigger and data acquisition performance, with great advantage for HLT and offline selections downstream, and eventually for physics analysis. This technological revolution will make it possible to use advanced pileup mitigations techniques, such as pileup per particle identification (PUPPI), already in the L1 reconstruction, reconceptualising jet algorithms for L1 trigger at hadron colliders. We present proof-of-principle studies on both physics and hardware performance of prototype jet algorithms foreseen by CMS for the HL-LHC.