GBT oriented firmware for Data Processing Boards for CBM

18 Sept 2018, 17:20
1h 30m
FBS 0.01/0.02 (Feestzaal)

FBS 0.01/0.02 (Feestzaal)

Poster Programmable Logic, Design Tools and Methods Posters

Speaker

Dr Wojciech Zabołotny (Institute of Electronic Systems, Warsaw University of Technology)

Description

The Data Processing Boards (DPB) are the important component of the development version of the CBM readout system. Even though in the final version they will be replaced with the new Common Readout Interface (CRI) PCIe boards, they are still used for development and testing of new firmware features and for operation during the beam tests.
The paper describes the current state of the DPB firmware development. The special emphasis is put on the functionalities related to support the GBTX-connected front-end electronics.

Summary

The concept of the CBM readout was significantly modified during the period of preparation of the experiment. In the last few years it was assumed that control of the FE electronics and reception of the data will be performed by the Data Processing Boards (DPB) implemented in the MTCA.4 technology.
The AFCK board was used as DPB prototype, and significant amount of work was put on development of its firmware.
Except of communication with FEE, the important task of DPBs is the transmission of the acquired and aggregated data via high-speed proprietary optical link to the computing center. According to the last trends in technology, in the new concept of the CBM readout, the MTCA.4 crates with DPB boards will be replaced with rack computers with PCIe Common Readout Interface (CRI) boards, allowing to use the COTS network technology for the link to the computing center.
However, the DPB boards are still playing the important role in the preparation of the CBM readout.
They are used to implement and test new readout IP cores and functionalities. They are also used in current hardware tests and beam tests.
The last developments include: support for commands with deterministic time of delivery, support for multiple FE ASICs connected via GBT links, aggregation and time sorting of the received hit data.
Necessity to work with different configurations of the Front End Boards (FEBs) has created a problem of configurable routing of the received data.
Significant increase of the internal complexity of the DPB firmware resulted in a necessity to create a mechanism, that extends standard IPbus methods of management of the address space.
The experimental nature of the DPB boards requires, that such parameters as the number of serviced FE ASICs or configuration of FEBs should be easily changeable.
Therefore, the DPB is a good example of the flexible and parametrized control and data processing firmware.

Primary authors

Dr Wojciech Zabołotny (Institute of Electronic Systems, Warsaw University of Technology) Mr Adrian Byszuk (Institute of Electronic Systems, Warsaw University of Technology) Dr David Emschermann (GSI-Helmholtzzentrum für Schwerionenforschung GmbH) Mr Marek Gumiński (Institute of Electronic Systems, Warsaw University of Technology) Dr Grzegorz Kasprowicz (Institute of Electronic Systems, Warsaw University of Technology) Joerg Lehnert (GSI - Helmholtzzentrum fur Schwerionenforschung GmbH (DE)) Pierre-Alain Loizeau (GSI - Helmholtzzentrum fur Schwerionenforschung GmbH (DE)) Walter Muller (GSI - Helmholtzzentrum fur Schwerionenforschung GmbH (DE)) Prof. Krzysztof Pozniak (Institute of Electronic Systems, Warsaw University of Technology) Prof. Ryszard Romaniuk (Institute of Electronic Systems, Warsaw University of Technology)

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