CRU Weekly Meeting

Wednesday 21 Feb 2018, 11:00 → 12:00 Europe/Zurich

CERN

 

• 10G PON (Mazsi is on leave)
• GBT
• DCS
• PCIe
  • News on the compilation issue with IP
• Integration
  • Preint was integrated with the other => now a single repo for the whole project
  • pcie40-v2 compiles up to synthesis, issues arise in fitter stage (see text file attached)
  • pcie40-v2 firmware requires
    • TTC-PON modification (to drive 2 transceivers)
    • PCIe modification to use two resets and two reference clocks
• Simulation
• Production
• Pending subject/ to do
  • News on the compilation issue with the PCIeDMA IP
  • IP for various target (dev kit, CRU V1, CRU V2)
    • Which solution? (see attached image in the case of CRU V2)
    • Have all IP in a single directory? Different directory per target? Regenerate IP for each target at each new clone?
  • Remove libraries in (and use component declaration and/or package) :
    • GBT core
    • ctpemu
    • onu_core
    • onu_user_logic,
    • pciedma.
  • Removal of CRU_misc library to be done by one person only, in a single day (impact on all modules) -> Olivier on feb 26/02.
  • Documentation on the TTC-PON and ONU core, connection with ONU design team?
  • Update of the specification and the requirement documentation
  • Regroup functionalities :
    • GBT related
    • TTC related
    • DCS related
• AOB

first_fitter_errors.txt

IP_variant.png

Present

Joel, Tivadar, Tuan, Pippo, Olivier

 

Many detectors are willing to start tests at the same time

• TPC :
  • several issues were found, but not reproduced in the lab, after reloading firmware it was OK
• DCS : Test with differents boards
• MCH : Will have a PRR review next month, so they need to collect data
• MID : They don't have a CRU, they work with GRORC, mainly on DCS.
• ITS :

 

 

10G PON

(Mazsi)

• On leave
• Merge to be done

 

GBT

(Erno)

• Standalone design was rebuild with the new GIT repository
• Busy with debugging Calcutta board
• Try to fix the external reference PLL clock for V1. On V2 it will be a different PLL anyway, but we need to understand the hardware issues (for general understanding)
  • We don't aim to use external jitter cleaning on the V1
• Tivadar : The use of the external clock system is not yet decided for V2. If internal PLL is fine, we won't use it. But we want to check what is the best quality we can achieve. For that the PLL should work with a 240 MHz recovered clock instead of using the 40 MHz.
• Please remove GBT core library

 

DCS

(Pippo)

• Mainkly working with sub-detectors, no news.

 

PCIe

(Pippo)

• QSYS could not be automatically generated by the make command.
• A temporary fix was to commit the generated files
• Now, it seems that using qsys-generate manually before typing make works and solves the issue. Makefile will be updated to add a make ip
• A problem was discovered with a CRU (low performances)
  • That means that working CRU exists, but that they are not performant enough! The cause of the problem is not clear hardware or firmware. Seems to be correlated with power module.
  • We have to check if there are many retransmitted packet
  • The TPC card has to be borrowed to run the same test and confirm that is correlated to old power modules. If it is they will be changed.

 

Datapath wrapper

(Olivier)

• Some documentation will be commited

 

Integration

(Olivier, all)

• Preint was integrated with the other => now a single repo for the whole project
• PCIe modification to use two reference clocks -> to be done latter on
• pcie40-v2 firmware requires two issues to be solved:
  • TTC-PON modification (to drive 2 transceivers) → Mazsi? At least after merging last modifications
  • pcie40-v2 compiles up to synthesis, issues arise in fitter stage (see text file attached)

 

Simulation

(Olivier)

• No news

 

Production

(Tivadar)

• First cards from India were tested
• Card #2 has a single issue left (PLL work well), GBT #13 does not work. The likely defective is a borken capacitor. If correct, it will be sent to CERN.
• One more new power module is available.
• Another card form india is in shipping, should arrive soon.

 

Travels/vacations

Feb 22-23 : Olivier on leave