Review Procedure

• Philippe Farthouat (CERN)

Room: 104/R-B09

Introduction & Review Scope

• Stephanie Ulrike Zimmermann (Albert Ludwigs Universitaet Freiburg (DE))

Room: 104/R-B09

Summary of Trigger processor requirements. Evolution since 2015 PDR.

• Verena Ingrid Martinez Outschoorn (University of Massachusetts (US))

Room: 104/R-B09

Mezzanine card v1 design & test results (hardware)

• Sorin Martoiu (IFIN-HH (RO))

Room: 104/R-B09

Mezzanine card v1 assessment of FPGA resources

• Nathan Felt (Harvard University (US))

Room: 104/R-B09

Carrier card v2 specifications

• Thiago Costa De Paiva (University of Massachusetts (US))

Room: 104/R-B09

Carrier card v2 design status & schedule

• Sorin Martoiu (IFIN-HH (RO))

Room: 104/R-B09

Thermal test results (carrier + mezz + ATCA)

• Thiago Costa De Paiva (University of Massachusetts (US))

Room: 104/R-B09