NSW Trigger Processor IDR

Tuesday 26 Jun 2018, 14:00 → 18:30 Europe/Zurich

104/R-B09 (CERN)

Reviewers:

• Philippe Farthouat (CERN)
• Stefan Haas (CERN)
• Xueye Hu (Michigan)
• Yao Lin (BNL)
• Tomoyuki Saito (Tokyo)
• Stefano Veneziano (Roma)

Ex-officio:

• Lorne Levinson (Weizmann)
• David Strom (Oregon)
• Stephanie Zimmermann (Freiburg)

2015 Design Review report

Mezzanine Specification

New Carrier Specification

Old Carrier specification

UpdatedJune2018_TriggerProcessorDRR.pdf

1 Review Procedure

Speaker: Philippe Farthouat (CERN)

2 Introduction & Review Scope

Speaker: Stephanie Ulrike Zimmermann (Albert Ludwigs Universitaet Freiburg (DE))

NSW_TP_Review_20180626.pdf

NSW_TP_Review_20180626.pptx

3 Summary of Trigger processor requirements. Evolution since 2015 PDR.

Speaker: Verena Ingrid Martinez Outschoorn (University of Massachusetts (US))

NSWTriggerProcessor_SpecsReview_MartinezOutschoorn.pdf

4 Mezzanine card v1 design & test results (hardware)

Speaker: Sorin Martoiu (IFIN-HH (RO))

tp_idr_mezz_sm.pdf

5 Mezzanine card v1 assessment of FPGA resources

Speaker: Nathan Felt (Harvard University (US))

Trigger Processor Resource Evaluation.pdf

Trigger Processor Resource Evaluation.pptx

15:50 Coffee

6 Carrier card v2 specifications

Speaker: Thiago Costa De Paiva (University of Massachusetts (US))

tcpaiva-nswtp-bladev2_specifications_idr-20180626.pdf

7 Carrier card v2 design status & schedule

Speaker: Sorin Martoiu (IFIN-HH (RO))

tp_idr_carrier2_status.pdf

8 Thermal test results (carrier + mezz + ATCA)

Speaker: Thiago Costa De Paiva (University of Massachusetts (US))

tcpaiva-nswtp-thermal_tests-idr-20180626.pdf