Pixel RCE Test stand tasks  (Nov/9/2009)


RCE test stand tasks: 
---------------------

1) Current ROD teststand setup documentation and demonstration of how individual 
calibrations run. 

   eBOC repair status. Can we run CERN teststand ? 

2) Calibration implementation

   ST control implemention 
  
   DSP code porting     

3) Description of the steps for the calibrations: nature and counts of the nested 
loops, how much data I/O at each step, what calculations at each step etc.  
Total data volume flow and CPU needs for calibration: could we ship data out to 
do calculations outside ?

   Any question regarding Matthias presentation from previous meeting ? Document this 
   information in a summary form ?    

4) Pixlib compatibility survey (import to Eclipse ? Netbins?) and structure classification 
proposal towards an agreed plan with with Paolo and Bonn teststand workers on
how DAQ framework would migrate to IBL era  

   Any news on code structure investigation to guide evolution ? Paolo's new pixlib release ?       
   Where to map th SBC code ? Interface to TDAQ.          

4) Test stand and hardware availability
   SLAC RCE access clarified ? 
   CERN RCE teststand reactivated. 
   More HSIO boards ? 
   Merged RCE+HSIO board   
 
5) RCE RTEM performance measurements for CPU consumption and memory access speed etc 
   data formating software slow ? best way to configuration endian flip ?  
   
   Try JJ's data formating code Data formatting code on digital scan.
   Endian flip and configuration speed up ? 
     
 
Activities to follow still:
---------------------------

* Initial port of DSP slave calibration code to RCE framework

* Debugging individual calibrations and implement performance improvements as 
needed to fully demonstrate all calibrations on FE-I3 modules (this needs 
many contributers to take responsibilities of individual calibrations) 
 
* Explore FPGA DSP tiles for calibration algorithm speed improvements    

* FE-I4 compatibility of calibration code. Can start exploring with FE-I4 emulator ? What
can the emulator do and what cannot do ?  


ROD design issues
-----------------

*  The stage by stage plan of the IBL strategy to not only scope out the eventual ROD system, 
but the earlier stage current tests board and prototypes which can serve the IBL frontend 
chip and proto stave tests much earlier. How far the current RCE board can be stretched to do 
all the tests including stave-0 tests and test beam ? 

*  TTC interface absorption int the CIM/RCE infrastructure. Can get get hold of large 
quantities of TTCrx ?

*  Frontend interface (BOC). How to do this generically to work for other subsystems too ?

*  What new hardware to build next ? S-link ? 

*  Followup on CSC muon example in more detail to verify common solutions.