Speaker
Description
The COMET experiment aims to search for the neutrinoless muon to electron transition process. The online trigger system is an integral part of reaching the sensitivity levels required and will be located in the detector region where high levels of neutron radiation are expected. Consequently a significant number of soft errors in the digital logic of the on board field programmable gate arrays (FPGA) can occur, requiring error correction for single event upsets (SEU) and firmware redownloading schemes for unrecoverable soft errors (URE). We tested the performance of one of the COMET Phase-I front-end trigger boards that implements a Xilinx Kintex-7 series FPGA, subject to neutron fluence up to $10^{12}\;n\;cm^{-2}$ with error correction and firmware redownloading schemes. Single bit and multi bit errors were measured in CRAM, BRAM and also in multigigabit (4.8 Gbps) cable transfer, with utilisation of multiple error correcting codes.
| Minioral | Yes |
|---|---|
| IEEE Member | No |
| Are you a student? | Yes |
