Olivier, Tuan, PiPPo, Erno, Joël, Tivadar.
- Test for power module are in progress
- Then will be shipped
- Not doing twice the same thing
- Tivadar asked Erno to do the logic filling test.
- Willing repeat the test with the released firmware
- We want to fill up the hardware go larger than previously
- It is parallel road to the development, no hardware needed at first, place and route only
- Erno wishes to validate good functionality, should be done in
- The safety for overheating should be in place and has not been challenged
What is the hardware limitation?
- PiPPo will check the available servers
- A google doc will be installed again if needed
- We have only 2 or 3 setups available
- Release officially announced
- Readout flow understood and validated
- EP issue located with some machine showing (when no bifurcation) it happens that the EP not connected to the dwrapper is used
- A register will be used to identify which EP is connected to what.
- One temporary fix.So we need to compile a single dwrapper and single PCIe EP to avoid issue with test
- TPC notified
- Waveform player
- we need to understand more the input of the wf player. Sync pattern was triggered, but why alternating pattern reset/idle
- cru-test validated
To do in the coming weeks
Go through the issue list, close and/or process those:
- Connect the DDG and check the data flow -> PiPPo
- Fix timing issues
- Save resource on GBT (gbt/gbtx, sharing) -> JB
- GBT Update avalon slaves to the new one -> JB
- GBT/SC Take out GBT sc from GBT and share it -> PiPPo
- Simply gbt clock interface to a single one -> all
- Move wfplayer in TTC
- to do after current testing with TPC
- Remove JTAGMMM? -> Olivier
- Core must be cleaned (generic and all ...) -> Olivier
- Only generic should stay is the number of links
- BSP (and move run_enable) -> Olivier
- flowstatistic understanding and simplification -> Tuan will do a readme.md, Oliver will take
- Find a way to simulate the core (main issue is the Pcie model) :
- find a way to replace lower level of altera model to speed up?
- clean all CDC things -> all, remove statcnt (use gen_counter)
- Topic about BAR address too large (issue #33)? -> all
- BAR0 : internal to PCIeDMA
- BAR2 is exported outside QSYS for the rest of the logic. Big jumps (too big). a factor of 2
Channel skew measurement
- Tuan showed a measurement proving that the skew between CRU and links is much less than expected by simulation → it is a very good news
CRU V1 support
PiPPo ask for dropping support on CRU#1 for now. Situation available
- 5 in the lab, 4 in Calcutta.
- No user, at exception of TPC, has a CRU V1.
- So for now we keep the folder and drop effort on that
Next week (july 11th) will be the last before summer, and we return to regular meetin in the second part of August
- PiPPo in CHEP next of week.
- Tuan in vacation from july 16th to july 30th
- Olivier : mid july to mid august, precise date to be given
There are minutes attached to this event.