Attendees
Olivier, Tuan, PiPPo, Tivadar.
Status
(Olivier)
- Work done on timing for TTC
- pma to rx_clk user easy, proposal made to Edurdo
- tx-clk to core more tricky, should be OK, but not possible to test yet
- => Ask Marian and/or Eduardo for a way to test the user side of the ONU (ideally a counter pattern) → Olivier
- Simplification of BSP and TTC was done and validated by Tuan and PiPPo
- Still timing issue with PCIe
- PiPPo propose to go for a single clock domain FIFO
- Tasks by the end of the week for Olivier
- In BSP preparation for run_enable → next thing to do in the comming days
- JTAGMMM removal at the same time
- Main avalon simplification (in core)
- CRU/FEE trigger protocol:
- Things did not clear up yet, even though Jo said that there is no issue with 8kB packet
- Olivier will recontact Jo to receive inputs to work on the CRU-FEE protocol
- User logic implementation
- No sign from TPC yet, Olivier will recontact them after his vacation to check the status (otherwise low support will be provided)
(PiPPo)
- Propose to remove the DMA part from the python script
- We will go for a py script to setup
- a shell or py script to start roc-bench and start data taking (see RUN enable mod)
- SCA documentation update to be done (see TPC request)
- DMA : Which endpoint is used will be reported soon (comming fix)
- qsys about to be dropped by Altera, will move to .ip, work in progress
- To all : remember to do a make ip_gen everytime the PCIEdma is touched (even if it is only VHDL)
- Slow control to be moved out of the GBT wrapper
- TPC will collect data soon
- Sync problem at startup to fix
- Software side
- PiPPo reported the required root account issue noted by TPC
- roc-list-card should be modified to the reported information, a new comer will be available in september.
- Hardware side
- Cards send to TPC, ITS, MFT, MID
- MCH and TOF will the next to receive some cards
- Keep a eye in TRD
- Think of a TRD wrapper?
- Have a TRD directory with most of the same files
- Lab setup
- 3 machines, each of them can program its own CRU (direct cable)
(Joel), reported by Olivier
- GBT shared pattern generator and avalon simplification in progress, should start testing by the end of the week
(Tuan)
- Working on the phase scanning to implement it in VHDL so that it will be automatic and faster
- Working to have automated measurement after resets (for statistics)
(Tivadar)
- The power module testing are finished
- The power module load test will be with CRU
- Next week is alice week, power module will be delivered to have 2 more CRU
- No news from cards in CPPM
- What about the firmware ressource test made by Erno:
- Olivier said difficult to draw conclusion, as much work is still required on the firmware, we need TPC input. Also the firmware had only minor resource saving yet, the big part still to come, these are:
- GBT_SC sharing
- Removal of the FEC and the dynamic switching for the GBT used by TPC
=> no more weekly meeting until after mid-august
Vacations
- PiPPo mostly there during summer
- Tuan not available for from 16th to end of july
- Olivier in vacation from 16th of july to 20th of august. Will be present a few days now and then but not reachable between 20th and of july.
- Tivadar will be around in summer and reachable.
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