Sep 12 – 17, 2021
University of Birmingham
Europe/London timezone

Timepix4 timestamping detector for synchrotron applications

Sep 13, 2021, 9:50 AM
15m
Teaching and Learning Building (University of Birmingham)

Teaching and Learning Building

University of Birmingham

Edgbaston Campus University of Birmingham B15 2TT UK
talk Detectors for FELS, Synchrotrons and Other Advanced Light Sources Detectors for FELS, Synchrotrons and Other Advanced Light Sources

Speaker

David Pennicard (DESY)

Description

Timepix4 is a versatile readout chip with 55 µm pixels, recently developed by CERN on behalf of the Medipix4 collaboration. It can operate both in a photon counting mode with frame readout, and a timestamping mode with event readout. Both of these modes offer higher performance than existing Medipix3 and Timepix3 chips. This makes Timepix4 appealing to a wide range of X-ray experiments at synchrotrons. For example, while X-ray diffraction experiments are normally done with framing detectors, the ability to switch to timestamping mode can offer extreme time resolution (down to individual synchrotron bunches) in experiments with moderate flux or specific regions of interest.

At DESY, a new readout system is being developed that is designed to cope with the chip’s high readout bandwidth (up to 162 Gbps per chip). Firstly, a single chip carrier board has been designed, produced and tested. The layout, flat and with the chip at the edge of the board, enables a number of experimental set-ups, and also allows for 2-chip tiled systems. For this first iteration, a commercially available readout board hosting a powerful Zynq UltraScale+ System on Chip has been chosen, due the large number of high speed transceivers available. Data is transferred to a control PC over Firefly optical links. Firmware and software development and chip testing are in progress.

In the long term, multi-megapixel systems composed of multiple chips will be developed. New detector head boards and also custom readout boards will be needed. Furthermore, recent developments on Through Silicon Via (TSV) technology will make it possible to operate the chip without wire bonds, thus greatly reducing the dead gaps between modules.

Title Dr
Institute DESY
Your name David Pennicard
email david.pennicard@desy.de
Nationality UK

Primary authors

Presentation materials