Low jitter and radiation tolerant Phase-Lock-Loop (PLL) has been prevailingly researched and used in high-energy physics experiments. This paper presents the design and test results of a radiation tolerant, 4.5GHz to 5.6GHz PLL ASIC fabricated in 55 nm CMOS technology. The PLL ASIC consists of a phase frequency detector (PFD) circuit, a charge pump (CP) circuit, a low pass filter circuit (LPF), a LC voltage controlled oscillator circuit (LCVCO) with capacitor array, a feedback divider circuit and SPI module. In order to obtain low DC leakage current (about 500 pA) and reduce dynamic mismatch, the CP uses two unity-gain feedback operational amplifiers to keep the charge pump output common mode voltage constant. To obtain a wide range of frequency, the LCVCO can change the oscillation frequency by adjusting the capacitance value of the novel capacitor array. The tuning capacitor array consists of MOM capacitor units with three binary controlled NMOS switches and two big resistors. Besides, the LCVCO can improve the Q factor degradation due to the source/ drain leakage current from the binary controlled NMOS transistor.
The whole ASIC features a size of 1200 μm x 900 μm. The PLL covers a wide-frequency range from 4.5GHz to 5.6GHz, consuming a total power of 25 mW from the post layout simulation. At 5.12 GHz, the phase noise is -115 dBc/Hz @ 1MHz offset. The chip has been taped out and the tests are planned to be conducted in this May. The ASIC die will be glued and bonded to a high- frequency print circuit board (PCB) to which the DC supply voltage, SPI control signal and reference clock input can be applied. The electrical test and total ionizing dose (TID) test will be performed. The test results will be reported in the meeting.