Sep 2 – 6, 2019
Europe/Zurich timezone

A low-power mixed-signal ASIC for readout of SiPM at cryogenic temperature

Sep 5, 2019, 4:55 PM
Poster ASIC Posters


Mr Ramshan Kugathasan (INFN - National Institute for Nuclear Physics)


A mixed-signal ASIC developed to readout silicon photomultipliers (SiPM) at low temperature is presented. The chip is designed in a 110 nm CMOS technology. Both single photon counting and Time-over-Threshold (ToT) operating modes are supported. In single photon counting mode an event rate of up to 5 MHz per channel can be accommodated. The time resolution is 50 ps and the target power consumption is less than 5 mW per channel. The architecture of a first 32-channel prototype is described. Dedicated test structures to qualify critical building blocks at cryogenic temperature have also been deployed.


There is a growing interest in the use of Silicon photomultipliers (SiPMs) operating at cryogenic temperatures. The largely suppressed dark count rate observed at liquid Xenon and liquid Argon temperatures makes such sensors ideally suited to equip large area detectors like those needed in dark matter and neutrino experiments. Research programs to explore the possibility of building total body PET scanners based on noble liquids readout by SiPM are also ongoing.
ALCOR (A Low-power Circuit for Optical Readout) is a first prototype of a mixed-signal ASIC optimised for the readout of SiPMs at low temperature. The mixed-signal channel is implemented in an area of 440x440 um2 and can be configured to operate either in single photon counting or in Time-over-Threshold (ToT) mode. In the first mode, the arrival time of the single photons is recorded. The ToT mode is useful when many photons pile-up in the individual SiPM pixel and are treated by the electronics as a single continuous signal. Such a situation is common, for instance, in PET applications. In each channel, a regulated common-gate input stage acts as the interface between the sensor and the rest of the chain. Then the signal is conditioned by two amplifiers with programmable gain and shaping time. Two leading edge discriminators with configurable threshold generate the trigger CMOS signals that are fed to the channel digital control block. A coarse time stamp, derived from a binary 15-bit counter on-channel, is generated while four low-power time-to-digital converters (TDCs), generate the fine counter information of 9-bit. The clock frequency can be up to 320 MHz. In this condition, the TDCs have a binning of 50 ps and a dead-time of 150 ns. Data generated is a 32-bit payload that includes the time-stamp, the channel ID, and the specific TDC address. Generated data are collected to the periphery and transmitted off-chip using 4 LVDS drivers.
The design of chips working at cryogenic conditions entails several issues. The increased carriers mobility at low temperature may induce an accelerated device ageing. This can be partially mitigated by avoiding minimum length transistors and/or reducing the power supply voltage. Furthermore, transistor and digital standard cells are usually not modelled below -40 °C. To gain useful insights in view of the design of the ALCOR chip, dedicated test structures were fabricated. These include a copy of the front-end amplifier, a bandgap reference voltage, LVDS transmitters, basic digital gates, a clock buffer and a synchronisation circuit. The characterisation work is ongoing. The ALCOR design will be then finalised and optimised using inputs provided by the results obtained on the test structures. At the conference, the experimental results of the test structures will be presented and the architecture of the ALCOR chip will be discussed in detail in the poster.

Primary author

Mr Ramshan Kugathasan (INFN - National Institute for Nuclear Physics)

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