The ATLAS experiment will get a new inner tracker (ITk) during the phase II upgrade. The innermost part will be a pixel detector. A new Detector Control System (DCS) is being developed to provide control and monitoring of the ITk pixel detector. The DCS Controller is a CANopen based Application Specific Integrated Circuit foreseen to independently monitor a serial power chain. The final chip is required to be radiation hard up to an ionizing dose of 500 Mrad. In this talk, the functionality of the chip will be discussed and also results from the first test chip will be presented.
The Large Hadron Collider (LHC) will be upgraded to the High Luminosity LHC which also requires experiments to be upgraded. The ATLAS experiment will get a new full silicon inner tracker. The innermost part of the ATLAS experiment is the pixel detector. After the upgrade, the pixel detector will have 5 times more modules than the present state. A serial powering scheme has been proposed to reduce the number of services inside the detector volume. There are multiple serial powering chains and each chain can have a maximum of 16 modules connected in series. The Detector Control System (DCS) provides control/monitoring capability and also ensures the safety of the experiment.
The DCS system has three independent paths which are diagnostics, control & feedback, and safety. The diagnostics path provides high granularity data generated by the Front-End (FE) chips for debugging and fine-tuning of the system. The control & feedback path provides the main user interface to operate the detector. Power supplies provide control per serial power chain whereas the DCS controller provides information per detector module. The DCS controller must provide monitoring information even when the detector is not running. The Safety path is the hardwired interlock path which directly acts on the power supplies and has the highest reliability.
The DCS Controller is an ASIC foreseen to be used in the control & feedback path and has the same radiation tolerance requirements as the FE chip. The DCS Controller chip will have an ADC with a resolution of 12 bits and up to 40 channels to read voltages and temperatures of each module in the serial powering chain. The voltage across an individual module is read using a voltage divider circuit. The temperature of the modules is given by reading NTCs available on each module. This NTC is connected via an external pull-up resistor to the reference voltage provided by the chip.
The DCS controller communicates to the main server over Controller Area Network (CAN) bus using an integrated CAN controller and a physical layer. The core logic of the DCS Controller chip is the bridge controller to implement the hardwired version of the application layer CANopen protocol which is normally implemented in software. Both of these protocols are being implemented in a 2x2 mm2 chip which is also required to be radiation hard up to a total ionizing dose of 500 Mrad. Other components in the chip include CAN physical layer, Power-on-Reset, band-gap circuit, voltage regulators and an oscillator. This chip is designed using TSMC 65 nm technology and implements 5V circuits using core transistors.
The first test chip includes voltage regulators and the physical layer for the CAN bus while the first prototype of the digital logic has been implemented on an FPGA. In this talk, we present the development of the DCS Controller, the results from the first test chip and the FPGA implementation.