Sep 2 – 6, 2019
Europe/Zurich timezone

The first ASIC prototype of a 28 nm time-space front-end electronics for real-time tracking

Sep 3, 2019, 5:20 PM
Poster ASIC Posters


Mr Lorenzo Piccolo (Politecnico and INFN Torino)


A front-end ASIC for 4D tracking is presented. The circuit includes a charge-sensitive amplifier, a discriminator with programmable threshold, and a time-to-digital converter. A prototype has been designed and integrated in 28 nm CMOS technology. The presented design is part of a project aiming at reaching a high resolution both in space and in time, to provide front-end circuitry suitable for next generation colliders.


The next generation of colliders will produce a large number of events, and therefore will require a more tight selection of data to be stored for off-line analysis. Future track triggers should be able to perform a tight selection of events, even in case of high pile-up (150 to 200) and high background noise. The problem of track recognition can be simplified by adding time information to spatial information, thus providing ‘4D’ data at the pixel output. The track trigger will use both time and space information, to reconstruct tracks with better accuracy.
The TimeSPOT project, funded by INFN, aims at the development of a complete processing chain for particle detection with high resolution, both in space (< 100 µm) and in time (< 100 ps). The project will exploit the potential of 3D detectors, made either of silicon and of diamond, and will take advantage of the high speed and of the radiation hardness performance provided by the 28 nm CMOS technology.
This communication describes the read-out electronics and the design of the first silicon prototype for the TimeSPOT project. The ASIC has been designed in 28 nm CMOS technology, and includes all the relevant blocks of the front-end: charge amplifier and shaper, discriminator, time-to-digital converter, and output interface.
The first stage of the chain is a Charge Sensitive Amplifier (CSA) capacitively matched with the sensor. The CSA includes a sensor leakage current compensation, and its output signal is compared with a programmable voltage threshold, provided by a 6-bit DAC. The time difference between this pulse and a reference clock is digitized by a time-to-digital converter, and the resulting data is sent off-chip by a serial output with Low-Voltage Differential Signalling (LVDS) interface.
In the first prototype, circuit blocks can be characterized individually, or they can be connected together to form a processing chain. The architecture of the chip and the results of prototype characterization will be addressed in the presentation.

Primary authors

Sandro Cadeddu (Universita e INFN, Cagliari (IT)) Luigi Casu (Universita e INFN, Cagliari (IT)) Adriano Lai (Universita e INFN, Cagliari (IT)) Prof. Massimo Barbaro (Università di Cagliari and INFN Cagliari) Dr Corrado Napoli (Università di Cagliari and INFN Cagliari) Dr Stefano Sonedda (Università di Cagliari and INFN Cagliari) Luca Frontini (INFN and Università degli Studi di Milano) Valentino Liberali (Università degli Studi e INFN Milano (IT)) Alberto Stabile (Università degli Studi e INFN Milano (IT)) Angelo Rivetti (Universita e INFN Torino (IT)) Mr Lorenzo Piccolo (Politecnico and INFN Torino) Seyed Ruhollah Shojaii (University of Melbourne (AU))

Presentation materials

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