The ATLAS Inner Detector will be completely replaced by an all silicon tracker for the LHC upgrades in the mid 2020s. The increased resolution and data output rate of the innermost layers of the upgraded detector will require more cables that are low-mass and capable of multi-gigabit transmission.
An FPGA Mezzanine Card (FMC) was developed to interface with an FPGA and a cable bundle to measure crosstalk and bit error rate. We present the design of the cable bundle and the FMC, as well as the firmware used to drive the data and measure bit error rate.
The LHC will undergo upgrades in energy and luminosity in the mid 2020s. The ATLAS Inner Detector will be completely replaced by an all silicon tracker, and a new Pixel readout chip will be developed with decreased pixel size in the innermost layers to increase resolution, as well as an increase in data output rate from 160 Mbps to multi-gigabit transmission.
More readout channels in the detector will require more cables to transmit data on- and off-detector. The cables must be low-mass to fit in the limited space of the detector, as well as to minimize material within the volume. The high radiation environment precludes the use of optical links within the innermost layers. Twisted pair is being explored as an option for electrical data transmission in this region.
Multi-gigabit transmission on small gauge cables was tested previously at the Santa Cruz Institute for Particle Physics . Electrical pickup was measured on a single 36 gauge twisted pair cable as a function of distance from an aggressor cable. A promising performance of 5 Gbps transmission was observed. One cable was driven at a time and a nearby cable probed for pickup. In a cable bundle, many cables are transmitting data that is not necessarily coherent. Confirmation is required that significantly more cross-talk does not result. The response of a differential configuration to crosstalk under these conditions is also of interest. Thus a testing scheme involving FPGA driven LVDS transmission across of bundle of 8 cables is presented in this poster.
An FPGA Mezzanine Card (FMC) has been developed to interface with an FPGA and a bundle of eight 36 gauge cables with drain wire and aluminum foil shield. This poster presents the design of the hardware for this test setup including the cable bundle and the FMC, as well as the development of the firmware to drive data streams along cables and to measure bit error rate introduced by crosstalk.