Sep 2 – 6, 2019
Europe/Zurich timezone

High-speed design : how to successfully address the high speed challenges : 25Gbps and over

Sep 4, 2019, 10:45 AM
Aula magna

Aula magna

Oral Invited


Jean-Michel CAPITAN (Hardware Expert, CCES)


Today communication protocols (32Gbps PCIE Gen5, 112Gbs PAM4, ...) and FPGAs transceivers speeds are pushing
designer to hardware designs constraints, PCB material choice and layout constraints that where almost never considered years ago.
This presentation is an extract of a CCES technical training, and its purpose is to cover some of the theorical aspects of "high speed",
as well as some tricks and traps to be successfull in those coming designs.

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