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Analysis of multiple cell upset characteristics for logical circuits in radiation environment

Dec 14, 2019, 2:57 PM
1m
POSTER - Sun: B1F-Meeting room#3, B2F-RAN1/2; Mon-Wed: B1F Meeting rooms #5-6 (International Conference Center Hiroshima)

POSTER - Sun: B1F-Meeting room#3, B2F-RAN1/2; Mon-Wed: B1F Meeting rooms #5-6

International Conference Center Hiroshima

Peace Memorial Park, Hiroshima-shi
POSTER Radiation damage and radiation tolerant materials POSTER

Speaker

Dr Lili Ding (State Key Laboratory of Pulsed Radiation Simulation and Effect, Northwest Institute of Nuclear Technology)

Description

With the design and fabrication of integrated circuits entering the deep-submicron and nano-scale era, the possibility of radiation induced multiple cell upset (MCU) increases noticeably. Extracting the MCU characteristics (size, proportion, etc) from the observed radiation-induced upsets can provide useful information for designing hardening strategies and fault injection experiments, which is of great importance for both storage circuits and logical circuits. For logical circuits composed of storage cells (DFF, etc) and combination logic gates (inverter, NAND, etc), the recorded information during irradiation only consist of upset counts but without the corresponding addresses. It is not easy to identify the MCU size and the corresponding proportion information as storage circuits.

In this work, a statistical analysis procedure of MCU characteristics in logical circuits was proposed. Our contributions focus on extending MCU feature extraction from storage circuits to logical circuits. Meanwhile, besides the geometrical progression distribution proposed in the reference, Gaussian distribution was proposed, verified, and implemented in MCU study to describe the condition when more than 1-bit upset dominates. When developing the model, a lot of data from references were adopted, with the Device under Test (DUT) of 150nm, 90nm, 65nm, and 25nm feature sizes. The choice of average upset counts in each read cycle was recommended, to reach an estimation accuracy within 20%. In this way, we may evaluate the MCU characteristics in logical circuits, both upsets due to cells and burst upsets due to global resources.

Submission declaration Original and unpublished

Primary author

Dr Lili Ding (State Key Laboratory of Pulsed Radiation Simulation and Effect, Northwest Institute of Nuclear Technology)

Co-authors

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