A SEL Sensitive Area Testing System for Integrated Circuits Based on the MAPS Detector

Dec 14, 2019, 3:03 PM
1m
POSTER - Sun: B1F-Meeting room#3, B2F-RAN1/2; Mon-Wed: B1F Meeting rooms #5-6 (International Conference Center Hiroshima)

POSTER - Sun: B1F-Meeting room#3, B2F-RAN1/2; Mon-Wed: B1F Meeting rooms #5-6

International Conference Center Hiroshima

Peace Memorial Park, Hiroshima-shi
POSTER Radiation damage and radiation tolerant materials POSTER

Speaker

Mr Fan Shen (Central China Normal University)

Description

Many electronic systems are designed to work in the environment of radiation and should have the radiation tolerance ability. Particularly the Single Event Effect (SEL) could induce the latchup of CMOS Integrate Circuits (IC) and degrade the device functionality. Therefore, the study of test methods for SEL sensitive area of integrated circuits becomes an important subject which helps us analyze the ability of anti-radiation and guides radiation hardening.
The traditional position systems for latchup are mainly based on microbeams or lasers and need mechanical devices with high precisions to move the injection spot of particles or the position of the device to be radiated. However, the system has some drawbacks: difficult to manufacture, expensive, time-consuming and inefficient. The Monolithic Active Pixel Sensor (MAPS) has advantages of high spatial resolution, thin materials, strong anti-radiation and mature fabrication technology, which make it a suitable candidate for particle tracking. We developed a camera based on MAPS to obtain a latchup map that reveals the distribution of SEL sensitive areas of integrate circuits. The MAPS detector records the incident position of the particles and the system determines the time when latchup occurs. The statistical method is used to calculate the probability of latchup of each small area. The TOPMETAL-III, used in this system, is a MAPS detector designed independently by Central China Normal University and its core functional block is a matrix composed of (512 rows x 256 columns) pixels, with 40 µm pitch, for a chip size of 2.3 cm x 1.2 cm. It has 300 kRad anti-radiation capabilities, with thickness less than 50µm, and is manufactured with the GSMC 0.13µm process. The system will be tested on the Heavy Ion Research Facility at Lanzhou, China (HIRFL) by particles of $^{86}Kr$ with 25MeV/u energy. Meanwhile other related subjects have been researched: mechanism of protecting the MAPS, algorithm of generating probability density of latchup, the influence of beam type and strength on the test precision, the detection method of latchup and so on.

Submission declaration Original and unpublished

Primary authors

Mr Fan Shen (Central China Normal University) Dong Wang (Central China Normal University CCNU (CN)) Pengcheng Ai (Central China Normal University) Mr Deli Xu (Central China Normal University) Mr Ni Fang (Central China Normal University) Mr Hui Wang (Central China Normal University) Junling Chen (Central China Normal University CCNU (CN))

Presentation materials