Monolithic CMOS sensors for sub-nanosecond timing

Dec 14, 2019, 2:25 PM
1m
POSTER - Sun: B1F-Meeting room#3, B2F-RAN1/2; Mon-Wed: B1F Meeting rooms #5-6 (International Conference Center Hiroshima)

POSTER - Sun: B1F-Meeting room#3, B2F-RAN1/2; Mon-Wed: B1F Meeting rooms #5-6

International Conference Center Hiroshima

Peace Memorial Park, Hiroshima-shi
POSTER Pixel sensors for tracking POSTER

Speakers

Thanushan Kugathasan (CERN) Prof. Takeharu Etoh (Ritsumeikan University)

Description

In the ATTRACT project FASTPIX we investigate monolithic pixel sensors with small collection electrodes in CMOS technologies for fast signal collection and precise timing in the sub-nanosecond range.

Deep submicron CMOS technologies allow tiny, sub-femtofarad collection electrodes, and large signal-to-noise ratios, essential for very precise timing. However, complex in-pixel circuits require some area, and one of the key limitations for precise timing is the longer drift time of signal charge generated near the pixel borders. Laying out the collection electrodes on a hexagonal grid and reducing the pixel pitch minimize the maximum distance from the pixel border to the collection electrode. The electric field optimized with TCAD simulations pulls the signal charge away from the pixel border towards the collection electrode as fast as possible. This also reduces charge sharing and maximizes the seed pixel signal hence reducing time-walk effects. Here the hexagonal geometry also contributes by limiting charge sharing at the pixel corners to only three pixels instead of four. We reach pixel pitches down to about 8.7 micron between collection electrodes in this 180 nm technology by placing only a minimum amount of circuitry with the pixel and the rest at the matrix periphery.
Consuming several tens of micro-ampere per pixel from a 1.8 V supply offers a time jitter of only a few tens of picoseconds. This allows detailed characterization of the sensor timing performance in a prototype chip with several mini-matrices of 64 pixels each with amplifier, comparator and digital readout and some additional pixels with analog buffers. The aim is to prove sensor concepts before moving to a much finer line width technology and fully integrate the readout within the pixel at lower power consumption.
The paper will present detailed TCAD simulation results and give an overview of the test chip with an outlook on finer line-width technologies. The development of a pyramidal structure micro-machined in silicon to further accelerate the charge collection and the time resolution of the sensor will also be presented.

Submission declaration Original and unpublished

Primary author

Co-authors

Dominik Dannheim (CERN) Prof. Takeharu Etoh (Ritsumeikan University) Magdalena Munker (CERN) Heinz Pernegger (CERN) Angelo Rivetti (INFN - National Institute for Nuclear Physics) Prof. Kazuhiro Shimonomura (Ritsumeikan University) Walter Snoeys (CERN)

Presentation materials