The proposed Circular Electron Positron Collider (CEPC) imposes new challenges for the vertex detector in terms of material budget, spatial resolution, readout speed, and power consumption. CMOS Pixel Sensor (CPS), as one of the promising candidate technologies, has been studying within the CEPC vertex detector R&D activities since 2015. According to the latest collider design and study on the beam-induced background, the highest hit rate for the vertex detector is expected to be ~107/cm2/s. In addition, the readout system should meet the 25 ns bunching spacing for the Z pole. A CPS prototype with a high data rate (120 MHz) has been developed in a 180 nm CMOS process. This talk presents the dedicated improvements on the design of in-pixel readout to achieve a pixel pitch of 25 μm and a fast readout capability of 40 MHz. The analog front-end is derived from the ALPIDE (ALice Pixel DEtector) chip. Improvement on the analog front-end is made to obtain a faster-rising edge with a time walk less than 25 ns. Moreover, two new fast in-pixel digital readout designs have been implemented: an FE-I3-like scheme and an ALPIDE-like scheme. The two variations employ the same double-column drain architecture. In the FE-I3-like pixel, some modifications on the pixel address generator are made to save area. In the ALPIDE-like logic, the hit storage registers have been replaced by an edge-triggered flip-flop, leading to a smaller pixel size and preventing repeated hit readout before the analog front-end resets. The priority address encoder block has been modified to boost its speed to 40 MHz. When a hit is detected in one of the pixels, the end of column circuitry stores the current time stamp with a resolution of 25 ns. The data whose timestamp matches with the trigger (with a time window of 175 ns) are buffered for output in case of trigger mode. The designed prototype is in fabrication and expected to be characterized this November.
|Submission declaration||Original and unpublished|