Oct 13 – 18, 2019
Lafodia Sea Resort, Lopud Island, Croatia
Europe/Zurich timezone

Serial Powering for the Tracker Phase-2 Upgrade

Oct 17, 2019, 11:00 AM
Lafodia Sea Resort, Lopud Island, Croatia

Lafodia Sea Resort, Lopud Island, Croatia


Dominik Koukola (CERN)


The upgrade of the Large Hadron Collider for the High-Luminosity (HL-LHC) phase, will introduce extreme operating conditions for the CMS Inner Tracker, including hit rates of 3.2 GHz/cm2 and a trigger rate of 750 kHz. The radiation levels will be reaching the unprecedented levels of 1.25 Grad of Total Ionizing Dose (TID) and a hadron fluence of 2.3×10^16 neq cm−2 for 10 years of operation. In addition, there are very tight physical constraints on the available space for the services as well as stringent material requirements posed in order to maintain good tracking performance. Therefore, a new and highly efficient, low mass Inner Tracker detector is being designed and will be installed in CMS to fully exploit the physics potential of the upgraded machine.

The Inner Tracker detector will be made of 3900 hybrid modules i.e. silicon sensors bump-bonded to pixel readout chips (two or four). Both thin planar and 3D silicon sensors are being considered with a pixel aspect ratio of 25x100 um2 or 50x50 um2. The pixel readout chip demands a deep sub-micron CMOS technology and an efficient architecture, where groups of pixel channels will share digital resources for buffering, control and data formatting. A large demonstrator pixel readout chip, the RD53A, has been designed by the RD53 collaboration in 65 nm CMOS technology addressing all the above-mentioned challenges. The use of this modern high density low power CMOS technology with low supply voltage (1.2 V), demands significant current levels of about 2 A per chip, resulting in a total of 40 kW needed to power the final pixel readout chips, the design of which will be submitted in spring 2020.

A serial power distribution scheme is the only viable solution to supply the HL-LHC pixel detectors with the required current levels, within acceptable material budget and power cable losses. In serial powering, a constant supply current is provided to a chain of modules (up to twelve) powered in series, while the chips on a module (two or four) are connected in parallel. To support this scheme, on-chip shunt-regulators are needed to generate locally the required voltages for the pixel chip. The RD53A chip has two integrated, radiation hard, and highly specialized and optimized Shunt-Low Dropout (Shunt-LDO) regulators, one per power domain (analog and digital).

The presentation will describe laboratory tests and results that demonstrate a reliable and efficient operation of this novel serial powering scheme. An overview of its implementation for the future CMS Inner Tracker and respective developments will be given. System tests performed on serial power chains of prototype RD53A quad modules, which host four RD53A chips on a high-density interface (HDI), will be presented. In addition, results from tests of failure analysis in chains of RD53A chips will be shown including reliability studies of the Shunt-LDO regulator. Finally, new Shunt-LDO features and improvements towards the final design of the CMS pixel chip will be discussed and remaining open points for the optimization of serial powering in CMS will be addressed.

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