Abstract
The LHCb experiment envisages to upgrade its readout electronics in order to increase the readout rate from 1 MHz to 40 MHz. This electronics upgrade is very challenging, since readout boards will have to handle a higher number of serial links with an increased bandwidth. In addition, the new communication protocol (GBT) developed by the CERN micro-electronics group mixes data acquisition, slow control and clock distribution on the same link. To explore the feasibility of such a readout system, elementary building blocks have been studied. Their goals are multiple: understand signal integrity when using highly integrated high speed serial links running at 8 - 10 Gbits/s; test the implementation of the GBT protocol within FPGAs; understand advantages and limitations of commercial standard with a predefined interconnection topology; validate ideas on how to control easily such a system. We designed two boards compliant with the xTCA standard which meets an increasing interest in the physics community. The first one is a generic handling 32 high speed serial links. The second one is a communication switch allowing the generic boards to communicate together. In this paper, we present jitter measurements obtained at 8 Gbits/s on serial link. We describe the versatility of this architecture which can be tuned from basic acquisition systems to more high-end complex ones. Finally, we demonstrate the feasibility of a low cost scalable control system based on NIOS core embedded in FPGAs.
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