A telescope for a beam test have been developed and it is described. This system is intended to carry out both analogue charge collection and spatial resolution measurements with different types of microstrip or pixel silicon detectors in a beam test environment.
The telescope has four XY measurement as well as trigger planes (XYT board) and it can accommodate up to twelve devices under test (DUT board). The DUT board uses two Beetle ASICs for the readout of chilled DUT (strip or fanout pixel silicon detectors). The board could operate in a self-triggering mode providing analogue and digital pulses for the readout system. The board features a temperature sensor attached to the DUT backplane via the copper chuck. The DUT can be mounted on a rotary stage controlled manually or by software. A peltier element is used for cooling the DUT. There is a provision of air fans for the heat sink of the Peltier element and a USB temperature controller.
The XYT board triggers on the particle tracks in the beam test and it measures the track space points using two silicon strip detectors mounted back-to-back at 90 degrees. The coordinate measurements are carried out with two Beetle ASICs. The card can also produce analogue and digital trigger pulses. It includes a CPLD which allows for the synchronization of the trigger signal to a common clock frequency, delaying and implementing coincidence with other XYT cards.
An Alibava mother board is used to read out and to control each XYT/DUT board from a common trigger signal and clock signal. The Alibava board has a TDC on board to have a time stamp of each trigger. The FPGA hardware description of the Alibava mother board have been adapted for this telescope. The data collected by each Alibava board is sent to a master card by means of a local data/address bus following a custom digital protocol. The USB controller for each Alibava mother board have been replaced by a digital connector and a readout bus terminator for this digital communication.
The master card distributes the trigger, clock and reset signals. It also merges the data streams from up to sixteen Alibava boards and it is in communication with the DAQ software via 100M Ethernet. The board has also a test channel for testing in a standard mode a XYT or DUT card. This board is implemented with a Xilinx development board and a custom patch card. New functionalities can be added to the master card by means of a new FPGA hardware description.
The power distribution for the system is carried out by means of a standard PC power supply and a power distribution card. The purpose is to fanout + 5V and +12 V to all Alibava systems and to the master card, scintillation trigger, DUT rotation stage and air coolers for the Peltier element of the DUT.
The DAQ software have been programmed in C++ and is based in the DAQ software of the Alibava system.