Abstract
We present a 16 channel front end prototype implemented in 90nm CMOS IBM process and optimized for 5pF input capacitance. The primary motivation for this project is to study the usefulness of the CMOS technologies below 130nm for front end amplifiers optimized for short strip silicon detectors in Super Large Hadron Collider (SLHC) experiments [1]. In the presented design we show critical aspects of the front end stages implemented in the deep submicron technologies. Particular effort has been put into minimization of the power consumed by the front end electronics. The nominal power consumption providing Equivalent Noise Charge (ENC) level below 1000e- for the chip loaded with 5pF input capacitance is around 220μW per channel.
Export citation and abstract BibTeX RIS