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14:00
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Review procedure
-
Hucheng Chen
(Brookhaven National Laboratory (US))
(Vidyo Only)
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14:10
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Introduction & Review Scope
-
Stephanie Ulrike Zimmermann
(Albert Ludwigs Universitaet Freiburg (DE))
(Vidyo Only)
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14:20
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Trigger Processor Firmware
(until 16:20)
(Vidyo Only)
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14:25
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Micromegas: L1A and readout (thru carrier). Algorithms and time alignment.
-
Thiago Costa De Paiva
(University of Massachusetts (US))
Nathan Felt
(Harvard University (US))
Nathan Felt
(Unknown)
(Vidyo Only)
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14:55
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sTGC stage-0: L1A and readout (thru carrier). Stage-0 algorithm; time alignment
-
Enrique Kajomovitz Must
(Department of Physics)
Enrique Kajomovitz Must
(Technion, Israel Institute of Technology)
(Vidyo Only)
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15:25
|
Merge block, and output formatter to SL.
-
George Chatzianastasiou
(University of Innsbruck (AT))
(Vidyo Only)
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15:55
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Results of combined tests with SL. Fixed latency. Latency measurements.
-
Lorne Levinson
(Weizmann Institute of Science (IL))
(Vidyo Only)
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16:20
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--- Coffee break and rest from staring on a screen ---
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16:35
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Carrier v3 design.Validation/test results (Bucarest/Samway, standalone)
-
Sorin Martoiu
(Horia Hulubei National Institute of Physics and Nuclear Enginee)
Andrei Scurtu
(Samway SRL)
(Vidyo Only)
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17:00
|
Board test protocol and procedures (for series production); acceptance criteria
-
Ricardo Di Curzio Lera
(University of Massachusetts (US))
Thiago Costa De Paiva
(University of Massachusetts (US))
(Vidyo Only)
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17:30
|
Production plan and schedule
-
Sorin Martoiu
(Horia Hulubei National Institute of Physics and Nuclear Enginee)
Mihai Savu
(Samway Electronic)
(Vidyo Only)
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18:05
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Installation plans @ P1 and commissioning
-
Alexander Naip Tuna
(Harvard University (US))
(Vidyo Only)
|