Digital calorimetry relies on a highly granular detector where the cell size is sufficiently small so that only a single particle in a shower enters each cell within a single readout cycle. The DECAL sensor, a depleted monolithic active pixel sensor (DMAPS), has been proposed as a possible technology for future digital calorimeters. A DECAL sensor prototype has been designed and fabricated in the standard TowerJazz 180 nm CMOS imaging process, using high resistivity 18 μm epitaxial layer. The prototype has a pixel matrix of 64x64 pixels with a pitch of 55x55 μm, and reads out using fast logic at 40 MHz. Each pixel contains four collection electrodes, trimming logic, pre-amplifier, shaper, comparator and discriminator with digital output. The pixel configuration logic provides a five bit calibration DAC and a mask flag. It can be reconfigured to function as either a strip sensor for particle tracking or a pad sensor, counting the number of pixels above threshold for digital calorimetry.
The talk will present results of chip characterisation, including digital summing logic, analogue pixel performance and threshold scans under laser illumination. The summing logic is tested using a test data shift register at the top of the pixel matrix that allows to inject a five bit number at the top of each column. The analogue pixel performance is validated illuminating a test pixel in the top left corner of the matrix with a laser with wavelength of 1064 nm. The performance of the digital pixels is less straight forward to evaluate as there is no direct readout available for individual discriminator output. Performing a threshold scan in columns and rows using trimming logic, the rate of hits in each pixel allows to test the full chain from analogue to digital. Laser illuminations in the digital pixel area and the response measured using a threshold scan confirm successful digital functionality in strip and pad operation mode. A new version of the DECAL sensor, has been designed and submitted for fabrication in the TowerJazz modified process with the aim to improve the Si sensor radiation hardness performance and the charge collection at the pixel edges. The variant chosen with a gap in the additional n- layer design for each pixel and expected to shape the electric field so the charge carriers produced are steered more directly towards the collection electrode in the pixel centre. In addition, the logic has been modified to have the pixel trim range extended from five to six bits, where the sixth bit will be for pixel mask flag which de-activates the in-pixel comparator.