The proposed architecture for the FGC4, which allows for remote voltage loops and interleaving between sub converters calculates the voltage loop on the same quad-core Xilinx SoC as the Current Loop. This additionally gives better integration of both loops, better logging and cost-optimised hardware. The index of the PWM will be sent from the processor to the FPGA which will generate the PWM signal.
It has been demonstrated that this approach can regulate at up to 200kHz (100kHz with full logging), for converters which require higher regulation rates the SIRAMATRIX-like solution would be implemented in the FPGA next to the generation of PWM. It has been demonstrated by CCE that a DSP is not required to generate the PWM.
It is proposed that CCS and CCE write, test and maintain the control loops from a specification written by the converter designer. The ability to adjust the loop parameters would be provided allowing the converter expert to tune the loop
Sources:
https://edms.cern.ch/ui/file/2710247/1/VARIANCE_ON_OPWR_SIGNALS_docx_cpdf.pdf