28nm Mixed-Signal Design Workshop

Name: 28nm Mixed-Signal Design Workshop
Start: 2023-01-30T01:30:00+01:00
End: 2023-02-03T17:00:00+01:00
Location: CERN

30 Jan 2023, 01:30 → 3 Feb 2023, 17:00 Europe/Zurich

572/R-013 (CERN)

572/R-013

CERN

ASIC Support Service (CERN), CERN EP-ESE

From the same series

2 3 4 5 6 7

Contacts

asic.support@cern.ch

https://asicsupport.web.cern.ch

Registration

Workshop on Analog and Digital design in 28nm registration

Surveys

Workshop on 28nm design survey

Monday 30 January
- Overview of the 28nm technology
  - 1
    
    Welcome
    
    Speaker: Alessandro Caratelli (CERN, EPFL)
    
    28nm_workshop_Wellcome.pdf
  - 2
    
    Technology Overview and designer’s guidelines
    
    Speaker: Franco Nahuel Bandi (CERN)
    
    28nm-workshop_Technology_Overview_and_Design_Guidelines.pdf
  - 3
    
    Overview of the 28nm common design platform
    
    Speaker: Marco Andorno (CERN)
    
    20230130_28nm_workshop.pdf
- 10:40
  
  Coffee break
- Overview of the 28nm technology
  - 4
    
    Total Ionizing Dose response of the 28nm technlogy
    
    Speaker: Giulio Borghello (CERN)
    
    Workshop on Analog and Digital design in 28nm - Radiation effects on 28nm CMOS technology.pdf
    
    Workshop on Analog and Digital design in 28nm - Radiation effects on 28nm CMOS technology.pptx
  - 5
    
    Single event effects hardening in digital design
    
    Speaker: Alessandro Caratelli (CERN, EPFL)
    
    28nm_workshop_SEE_Hardening.pdf
- 12:00
  
  Lunch break
- Analog design
  - 6
    
    Analog simulation with Explorer and Assembler
    
    Speaker: Helga Dornelas (Cadence)
- 14:45
  
  Coffee break
- Analog design
  - 7
    
    Lab session
    
    Speaker: Helga Dornelas (Cadence)
Tuesday 31 January
- Analog design
  - 8
    
    Mixed-signal simulation with Xcelium and Virtuoso
    
    Speaker: Helga Dornelas (Cadence)
- 10:15
  
  Coffee break
- Analog design
  - 9
    
    Lab session
    
    Speaker: Helga Dornelas (Cadence)
    
    28nm_mixed-signal_workshop_analog_fe_v04.pdf
- 12:00
  
  Lunch break
- Analog design
  - 10
    
    Analog Backend VXL Best Practices
    
    Speaker: Philippe Carriere (Cadence)
- 14:45
  
  Coffee break
- Analog design
  - 11
    
    Lab session
    
    Speaker: Philippe Carriere (Cadence)
    
    28nm_mixed-signal_workshop_analog_BE_v02.pdf
Wednesday 1 February
- Analog design
  - 12
    
    Lab session
    
    Speaker: Philippe Carriere (Cadence)
- 10:15
  
  Coffee break
- Analog design
  - 13
    
    DRC/LVS with PVS
    
    Speaker: Philippe Carriere (Cadence)
- 12:00
  
  Lunch break
- Analog design
  - 14
    
    Lab session
    
    Speaker: Philippe Carriere (Cadence)
- 14:45
  
  Coffee break
- Digital design
  
  28nm-workshop_synthesis_implementation_flat.pdf
  - 15
    
    Digital flow introduction
    
    Main steps of the flow, tools, Flowkit
    
    Speaker: Bertrand GENNERET (cadence design systems)
Thursday 2 February
- Digital design
  
  28nm-workshop_synthesis_implementation_flat.pdf
  - 16
    
    Block-level implementation
    
    Synthesis, floorplan
    
    Speaker: Bertrand GENNERET (cadence design systems)
- 10:15
  
  Coffee break
- Digital design
  
  28nm-workshop_synthesis_implementation_flat.pdf
  - 17
    
    Block-level implementation
    
    Placement, clock tree synthesis, routing
    
    Speaker: Bertrand GENNERET (cadence design systems)
- 12:00
  
  Lunch break
- Digital design
  
  28nm-workshop_synthesis_implementation_flat.pdf
  - 18
    
    Lab session
    
    Speakers: Alessandro Caratelli (CERN, EPFL), Bertrand GENNERET (cadence design systems), Marco Andorno (CERN)
- 14:45
  
  Coffee break
- Digital design
  
  28nm-workshop_synthesis_implementation_flat.pdf
  - 19
    
    Lab session
    
    Speakers: Alessandro Caratelli (CERN, EPFL), Bertrand GENNERET (cadence design systems), Marco Andorno (CERN)
Friday 3 February
- Digital design
  
  28nm-workshop_synthesis_implementation_flat.pdf
  - 20
    
    Hierarchical implementation
    
    Top level analysis with use of block model, assemble design
    
    Speaker: Bertrand GENNERET (cadence design systems)
- 10:15
  
  Coffee break
- Digital design
  
  28nm-workshop_synthesis_implementation_flat.pdf
  - 21
    
    Signoff
    
    Timing analysis, power analysis, DRC, LVS
    
    Speaker: Bertrand GENNERET (cadence design systems)
- 12:00
  
  Lunch break
- Digital design
  
  28nm-workshop_synthesis_implementation_flat.pdf
  - 22
    
    Lab session
    
    Speakers: Alessandro Caratelli (CERN, EPFL), Bertrand GENNERET (cadence design systems), Marco Andorno (CERN)
- 14:45
  
  Coffee break
- Digital design
  
  28nm-workshop_synthesis_implementation_flat.pdf
  - 23
    
    Lab session
    
    Speakers: Alessandro Caratelli (CERN, EPFL), Bertrand GENNERET (cadence design systems), Marco Andorno (CERN)