Name: 2nd FPGA Developers' Forum (FDF) meeting
Start: 2025-05-20T09:00:00+02:00
End: 2025-05-23T20:00:00+02:00
Location: CERN

Monday 19 May 2025
Tuesday 20 May 2025
14:00
14:00 - 15:10
Room: 500/1-001 - Main Auditorium
Contributions

14:00 Welcome to the 2nd FPGA Developers' Forum

14:20 Welcome to CERN

14:40 The future of FPGAs in HEP detectors for FCC and beyond - Sophie Baron (CERN)
15:10 Tea Break
Tea Break
15:10 - 15:40
Room: 500/1-001 - Main Auditorium
15:40
15:40 - 18:10
Room: 500/1-001 - Main Auditorium
Contributions

15:40 Open Logic – open-source FPGA Standard Library - Oliver Bründler (OpenLogic)

16:15 TBD - Calliope-Louisa Sotiropoulou (CAST)

16:45 The PandABlocks framework for flexible run-time configuration of Zynq SoCs - Glenn Christian (Diamond Light Source)

17:10 NDK: An open-source framework for high-speed network applications on FPGAs - Daniel Kondys (CESNET) Radek Iša (CESNET)

17:40 Error-Redundant Implementation of Commercial IP Cores: A Practical Example - Philipp Jacobsohn (SmartDV)
18:20 Welcome Reception
Welcome Reception
18:20 - 20:20
Room: 500/1-001 - Main Auditorium
Wednesday 21 May 2025
09:00 1
1
09:00 - 10:50
Room: 500/1-001 - Main Auditorium
Contributions

09:00 Exploring Linearity and Temperature Stability in Time-to-Digital Converters - Gian-Luca Brazerol (Ostschweizer Fachhochschule)

09:30 Implementation of Time to Digital Converter on FPGA for high-resolution-performance in Particle Therapy applications - ARASH AMINI BARDPAREH (Politecnico di Torino)

09:50 A low latency Gated Recurrent Unit Implementation for the AMD Versal AI Engine - Michail Sapkas (Universita e INFN, Padova (IT))

10:20 TBD
10:50 Coffee break
Coffee break
10:50 - 11:20
Room: 500/1-001 - Main Auditorium
11:20 2
2
11:20 - 12:50
Room: 500/1-001 - Main Auditorium
Contributions

11:20 Distributed Arithmetic for Real-time Neural Networks on FPGAs - Chang Sun (California Institute of Technology (US))

11:50 Chisel4ml: Generating Fast Implementations of Deeply Quantized Neural Networks using Chisel Generators - Jure Vreča (Jožef Stefan Institute)

12:20 A Reconfigurable FPGA-Based ML Library for Kernel Methods - Yousef Alnaser (TU Chemnitz, Fraunhofer ENAS)
12:50 Lunch
Lunch
12:50 - 14:00
Room: 500/1-001 - Main Auditorium
14:00 3
3
14:00 - 14:40
Room: 500/1-001 - Main Auditorium
Contributions

14:00 Accelerating Transformer Neural Networks on FPGAs for High Energy Physics Experiments - Filip Wojcicki (Imperial College London)

14:20 FPGA Implementation of Next-Generation Reservoir Computing for predicting dynamical systems - João Folhadela (Deutsches Zentrum für Luft- und Raumfahrt e.V. (DLR))
14:40 1
1
14:40 - 16:00
Room: 500/1-001 - Main Auditorium
Contributions

14:40 Abstract interface modelling for better genericity and code clarity - Nicolas Pouillon (Ellisys)

15:10 Disruptive Efinix Quantum Architecture - Harald Werner (Efinix Inc.)

15:40 CERN ABT's lazy git workflow for equipment-specific designs - Léa Strobino (CERN) Pieter Van Trappen (CERN)
16:00 Tea Break
Tea Break
16:00 - 16:30
Room: 500/1-001 - Main Auditorium
16:30 2
2
16:30 - 18:10
Room: 500/1-001 - Main Auditorium
Contributions

16:30 Low Jitter Frame Clock Recovery in Xilinx Ultrascale+ Transceivers - Paul Bachek (Brookhaven National Lab)

16:50 Standardizing SoC Development at CERN: A Build System for Xilinx Platforms - André Pinho (CERN)

17:20 Reset Usages in FPGAs - Koray Karakurt

17:50 The new CI4FPGA service at CERN - Christos Gentsos (CERN (IT-CA-GES))
20:00 Social Dinner
Social Dinner
20:00 - 23:20
Room: 500/1-001 - Main Auditorium
Thursday 22 May 2025
09:00 1
1
09:00 - 10:30
Room: 500/1-001 - Main Auditorium
Contributions

09:00 Application-Specific Arithmetic Operators with the FloPoCo HDL core generator - Florent de Dinechin (INSA-Lyon)

09:30 Customized eFPGAs with FABulous - Dirk Koch (Ruprecht-Karls-Universität Heidelberg)

10:00 Allo: A Python-Embedded Programming Model for Composable Accelerator Design - Hongzheng Chen (Cornell University)
10:30 Coffee break
Coffee break
10:30 - 11:00
Room: 500/1-001 - Main Auditorium
11:00 2
2
11:00 - 12:50
Room: 500/1-001 - Main Auditorium
Contributions

11:00 Generating memory maps with Cheby and Reksio - Bartosz Bielawski (CERN) Tristan Gingold (CERN)

11:20 HDLRegression: A reliable and efficient tool for FPGA regression testing - Marius Elvegård (Inventas)

11:50 Common Exchange Format for HDL Build Systems - Lieven Lemiengre (Sigasi)

12:20 nextpnr - customisable place and route for customisable silicon - Myrtle Shah (YosysHQ Gmbh)
12:50 Lunch
Lunch
12:50 - 14:10
Room: 500/1-001 - Main Auditorium
14:10
14:10 - 16:00
Room: 500/1-001 - Main Auditorium
Contributions

14:10 Enhancing FPGA Verification by Combining VUnit and UVVM - Markus Leiter (P2L2 GmbH)

14:40 TBD - Hardik Shah (Lattice Semiconductor)

15:10 Get the right FPGA quality through efficient Requirements Coverage (aka Specification Coverage) - Espen Tallaksen (EmLogic)
16:00 CERN Campus Visits
CERN Campus Visits
16:00 - 18:00
Room: 500/1-001 - Main Auditorium
Friday 23 May 2025
09:00 2
2
09:00 - 10:25
Room: 500/1-001 - Main Auditorium
Contributions

09:00 Python-based, flexible testbench for a spacecraft payload - Roberto Rigamonti (HES-SO/HEIG-VD)

09:25 Practical Methods for Functional Verification - Simone Ponzio (ARM)

09:55 High Performance FPGA Solutions – PRO DESIGN, best Choice for Development and Manufacturing - Bernhard Gleissner (proDesign)
10:25 Coffee Break
Coffee Break
10:25 - 10:55
Room: 500/1-001 - Main Auditorium
10:55 3
3
10:55 - 11:35
Room: 500/1-001 - Main Auditorium
Contributions

10:55 Why Your Team Should be using VHDL + OSVVM for Verification - Jim Lewis (SynthWorks)
11:35
11:35 - 13:05
Room: 500/1-001 - Main Auditorium
Contributions

11:35 Summary of FDF2025 and Awards

11:55 Closing Remarks