TB: BGI review outcome discussion

Europe/Zurich
866/2-D05 (CERN)

866/2-D05

CERN

30
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Zoom Meeting ID
69426758463
Host
Andrea Boccardi
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Action points:
James Storey:
  - Immediately order one pair of fibers for each of PS, SPS and LHC
BGI team :
  - Provide engineering specification
  - Keep pushing OP to provide functional requirements
  - Decide on an architecture.
    - Evaluate the hosted-SoC solution to see if it could be interesting (See with Federico Vaga, BE-CEM)
    - Evaluate capabilities of virtual CCR servers
  - See if Ethernet cables can be found which have better shielding than the current ones
Stephen Jackson:
  - Push for having support for acc-py on FECs


Discussions below:


Presentation on "BGI review outcome"
- James : OP continues to push to be able to get up to 1000 profiles per cycle on consecutive cycles.
- Thibaut : OP must provide functional requirements (needs a constant push from BI) for PS, SPS, LHC. BGI team must write engineering specification. Functional requirements should be reviewed against engineering specification, then organized and prioritized. We need to see what is possible. We cannot start an entirely new development as project resources are coming to an end.
- James : We have met repeatedly with OP. There is actually not much discrepancy. It remains to be seen if is technically possible to measure on consecutive cycles at 1000 profiles / cycle – so far this has not been achieved.
- Stephen/James : Approach should be to rapidly provide a reliable first version with basic functionality, then evolve from there adding more features.
- Thibaut : Requirements will evolve as we/OP get experience with using the system
- Tom : We must choose the architecture most likely to meet the requirement of 1000 profiles / cycle on consecutive cycles


Presentation on "EMC results & Plans"
- Mark : A ~20cm section of the HV cable is actually not shielded. We will improve cable shielding, add ferrites, improve faraday cage and add metal plate below instrument during YETS
- Tom : You should also see if other types of ethernet cables exist which have better shielding, even within cat6E cables there are different shielding levels. The PCB pins could also be a problem.
- Andrea : It could be interesting to compare your grounding approach to that used in LHCb
- Thibaut : You could perhaps get a high-frequency test environment in CLEAR
- James : We will investigate NXCALS data to see at what time we lose communication during AWAKE/LHC25NS cycles
- Andrea : You can look at timestamps to see when communication comes back.


Presentation on "BIPXL Architecture: Current and Future Options"
- Tom : Currently, you cannot have GPUs in CCR servers
- Stephen : GPUs are available in next generation of FECs
- Juri : In Javier's study it took at least 40ms to generate a single profile, even when using GPU => So 1000 profiles will take seconds to produces
- Manuel : These tests may have been done on outdated computers
- Stephen : Currently, acc-py is not supported on FECs but we should push for this
- Tom : acc-py is already being used on FECs "everywhere"
- Juri : It is not clear how many PCI lanes are available on the hosted-SoC solution (slide10, architecture3)
- Tom : You can consider using a dedicated ethernet to push raw data out of the SoC
- Manuel : We need the raw-data in files in order to do the machine learning
- All : Raw-data should not be pushed over TN
- Stephane : Virtual CCR servers are now available, with high network performance
- Stephane : You can also consider providing only "low-resolution" data during cycle and then "high-resolution" data at the end of cycle. It is always important to distinguish between the data that serves for visualization to OP and the data that is used computationally (with some degree of real-time)
- Tom : It is already too late to order fibers for LS3. We may have a few spares in SPS and LHC, but in PS I am not sure.
- Eva : I believe the deadline for ordering fibers has been extended to end of December.
- Tom : If you limit your request to one pair of fibers per accelerator (not per instrument) it might be accepted.
- James : I will make the request to EN-EL
- Tom : Concerning the hosted-SoC solution, EDGE drivers for PCI are not a problem - I have it running already. Similarly, IP cores for PCI communication are widely available.
- Andrea : Tom Wlostowski already has option3 (slide10) running.


Presentation on "Timeline"
Cancelled

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