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09:00
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Overview of the 28nm technology
(until 10:30)
|
|
09:00
|
Welcome
-
Alessandro Caratelli
(CERN)
|
|
09:20
|
Technology Overview and designer’s guidelines
-
Alessandro Caratelli
(CERN)
|
|
10:00
|
Overview of the 28nm common design platform
-
Marco Andorno
(CERN)
|
|
10:30
|
--- Coffee break ---
|
|
10:45
|
Overview of the 28nm technology
(until 12:00)
|
|
10:45
|
Total Ionizing Dose response of the 28nm technlogy
-
Giulio Borghello
(CERN)
|
|
|
09:00
|
Mixed-signal design
(until 10:30)
|
|
09:00
|
Lab session (Mixed-signal simulation)
-
Helga Uchoa Dornelas
|
|
10:30
|
--- Coffee break ---
|
|
10:45
|
Analog design
(until 12:00)
|
|
10:45
|
Analog Backend VXL Best Practices
-
Philippe Carriere
(Cadence)
|
|
11:00
|
Lab session (Analog backend)
-
Philippe Carriere
(Cadence)
|
|
|
09:00
|
Mixed-signal design
(until 10:00)
|
|
09:00
|
IP block integration (Liberty file and Abstract)
-
Marco Andorno
(CERN)
|
|
09:15
|
Lab session (Liberty file)
-
Marco Andorno
(CERN)
|
|
10:00
|
--- Coffee break ---
|
|
10:15
|
Digital design
(until 12:30)
|
|
10:15
|
Digital flow introduction
-
Mohamed Naeim
(Cadence Design Systems)
sebastien porte
|
|
10:45
|
Single event effects hardening in digital design
-
Alessandro Caratelli
(CERN)
|
|
11:30
|
Lab session (TMR)
-
Marco Andorno
(CERN)
Alessandro Caratelli
(CERN)
|
|
|
09:00
|
Digital design
(until 10:15)
|
|
09:00
|
Block-level implementation
-
Mohamed Naeim
(Cadence Design Systems)
sebastien porte
|
|
10:15
|
--- Coffee break ---
|
|
10:30
|
Digital design
(until 12:00)
|
|
10:30
|
Block-level implementation
-
Mohamed Naeim
(Cadence Design Systems)
sebastien porte
|
|
|
09:00
|
Digital design
(until 10:15)
|
|
09:00
|
Hierarchical implementation
-
Mohamed Naeim
(Cadence Design Systems)
sebastien porte
|
|
10:15
|
--- Coffee break ---
|
|
10:30
|
Digital design
(until 12:00)
|
|
10:30
|
Lab session (Hierarchical implementation)
-
Mohamed Naeim
(Cadence Design Systems)
sebastien porte
Marco Andorno
(CERN)
Alessandro Caratelli
(CERN)
|
|
|
12:00
|
--- Lunch break ---
|
|
13:30
|
Analog design
(until 15:15)
|
|
13:30
|
Analog simulation with Explorer and Assembler
-
Helga Uchoa Dornelas
|
|
13:50
|
Lab session (Analog simulation)
-
Helga Uchoa Dornelas
|
|
15:15
|
--- Coffee break ---
|
|
15:30
|
Mixed-signal design
(until 17:30)
|
|
15:30
|
Mixed-signal simulation with Xcelium and Virtuoso
-
Helga Uchoa Dornelas
|
|
16:00
|
Lab session (Mixed-signal simulation)
-
Helga Uchoa Dornelas
|
|
|
12:00
|
--- Lunch break ---
|
|
13:30
|
Analog design
(until 14:45)
|
|
13:30
|
Lab session (Analog backend)
-
Philippe Carriere
(Cadence)
|
|
14:45
|
--- Coffee break ---
|
|
15:00
|
Mixed-signal design
(until 15:50)
|
|
15:00
|
Abstract generation
-
Philippe Carriere
(Cadence)
|
|
15:20
|
Lab session (Abstract)
-
Philippe Carriere
(Cadence)
|
|
15:50
|
Analog design
(until 17:30)
|
|
15:50
|
DRC/LVS with PVS
-
Philippe Carriere
(Cadence)
|
|
16:10
|
Lab session (DRC/LVS with PVS)
-
Philippe Carriere
(Cadence)
|
|
|
12:30
|
--- Lunch break ---
|
|
13:30
|
Digital design
(until 15:15)
|
|
13:30
|
Timing constraints and synthesis
-
Mohamed Naeim
(Cadence Design Systems)
sebastien porte
|
|
15:15
|
--- Coffee break ---
|
|
15:30
|
Digital design
(until 17:30)
|
|
15:30
|
Lab session (Synthesis and LEC)
-
Mohamed Naeim
(Cadence Design Systems)
sebastien porte
Marco Andorno
(CERN)
Alessandro Caratelli
(CERN)
|
|
|
12:00
|
--- Lunch break ---
|
|
13:30
|
Digital design
(until 14:45)
|
|
13:30
|
Lab session (Block-level implementation)
-
Mohamed Naeim
(Cadence Design Systems)
sebastien porte
Marco Andorno
(CERN)
Alessandro Caratelli
(CERN)
|
|
14:45
|
--- Coffee break ---
|
|
15:00
|
Digital design
(until 17:30)
|
|
15:00
|
Lab session (Block-level implementation)
-
Mohamed Naeim
(Cadence Design Systems)
sebastien porte
Alessandro Caratelli
(CERN)
Marco Andorno
(CERN)
|
|
|
12:00
|
--- Lunch break ---
|
|
13:30
|
Digital design
(until 15:00)
|
|
13:30
|
Signoff
-
Mohamed Naeim
(Cadence Design Systems)
sebastien porte
|
|
15:00
|
--- Coffee break ---
|
|
15:15
|
Digital design
(until 17:30)
|
|
15:15
|
Lab session (Signoff)
-
Mohamed Naeim
(Cadence Design Systems)
sebastien porte
Alessandro Caratelli
(CERN)
Marco Andorno
(CERN)
|
|
