7th 28nm Mixed-Signal Design Workshop

Session

Digital design

19 Nov 2025, 10:15

593/R-013 (CERN)

17. Digital flow introduction

Mohamed Naeim (Cadence Design Systems), sebastien porte

19/11/2025, 10:15

Main steps of the flow, tools, Flowkit

6. Single event effects hardening in digital design

Alessandro Caratelli (CERN)

19/11/2025, 10:45

39. Lab session (TMR)

Alessandro Caratelli (CERN), Marco Andorno (CERN)

19/11/2025, 11:30

38. Timing constraints and synthesis

Mohamed Naeim (Cadence Design Systems), sebastien porte

19/11/2025, 13:30

40. Lab session (Synthesis and LEC)

Alessandro Caratelli (CERN), Marco Andorno (CERN), Mohamed Naeim (Cadence Design Systems), sebastien porte

19/11/2025, 15:30

18. Block-level implementation

Mohamed Naeim (Cadence Design Systems), sebastien porte

20/11/2025, 09:00

Synthesis, floorplan

19. Block-level implementation

Mohamed Naeim (Cadence Design Systems), sebastien porte

20/11/2025, 10:30

Placement, clock tree synthesis, routing

20. Lab session (Block-level implementation)

Alessandro Caratelli (CERN), Marco Andorno (CERN), Mohamed Naeim (Cadence Design Systems), sebastien porte

20/11/2025, 13:30

21. Lab session (Block-level implementation)

Alessandro Caratelli (CERN), Marco Andorno (CERN), Mohamed Naeim (Cadence Design Systems), sebastien porte

20/11/2025, 15:00

22. Hierarchical implementation

Mohamed Naeim (Cadence Design Systems), sebastien porte

21/11/2025, 09:00

Top level analysis with use of block model, assemble design

41. Lab session (Hierarchical implementation)

Alessandro Caratelli (CERN), Marco Andorno (CERN), Mohamed Naeim (Cadence Design Systems), sebastien porte

21/11/2025, 10:30

23. Signoff

Mohamed Naeim (Cadence Design Systems), sebastien porte

21/11/2025, 13:30

Timing analysis, power analysis, DRC, LVS

25. Lab session (Signoff)

Alessandro Caratelli (CERN), Marco Andorno (CERN), Mohamed Naeim (Cadence Design Systems), sebastien porte

21/11/2025, 15:15