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This tutorial introduces a practical workflow for deploying quantized neural networks on FPGAs using DA4ML (Distributed Arithmetic for Machine Learning). DA4ML, integrated into the hls4ml toolflow, replaces conventional multiply-accumulate operations with optimized distributed-arithmetic implementations, substantially reducing LUT consumption and latency for constant matrix–vector operations.
With HGQ, DA4ML forms a hardware-centric pipeline for producing deployable FPGA firmware from high-level neural-network descriptions. Participants will review how to quantize models with HGQ and learn how to generate FPGA designs with DA4ML, and evaluate performance trade-offs on realistic networks and target devices.