Comparison of Digital to Analog Converters in 0.20μum SOI and 0.13μm CMOS process

Not scheduled
1m
Sheraton Hotel (Chicago)

Sheraton Hotel

Chicago

301 East Water Street Chicago, IL 60611
Poster Presentation Front-end Electronics

Speaker

Michael Cooney (University of Hawaii)

Description

Biasing and threshold adjustments are crucial for the correct operation and sensitivity of 3T based pixel detectors. The latest generation of CAP detectors designed at the University of Hawaii addressed the threshold adjustment issue by including an 8-bit R-2R Digital to Analog converter. The DAC is the first designed at UH to be used in a 0.2μm SOI CMOS technology. The DAC has additionally been fabricated in a 0.13μm CMOS technology for characterization and use in digitizers presently being designed. The inclusion of such structure allows comparison between fabrication runs as well as fabrication technologies. Simulations and preliminary results are included, as well as comparisons between fabrication technologies.

Author

Michael Cooney (University of Hawaii)

Co-authors

Gary Varner (University of Hawaii) Larry Ruckman (University of Hawaii)

Presentation materials

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