SPS Timepix3-BGI DAQ - Part 2

Friday 4 Jun 2021, 10:00 → 12:00 Europe/Zurich

BGI Front-End Readout Planning: https://edms.cern.ch/document/2561213/1

• Quad GBTx board will be reused and connected to a motherboard with RJ45 connectors and FEAST modules for power
• One Quad GBTx board will provide 4x8x320 Mbit/s readout for 4x Timepix3 detectors
• Motherboard schematic in progress (Mark)

Zynq on BGI docs: https://bgi.docs.cern.ch/electronics/back-end/xilinx-mpsoc/xilinx-mpsoc/

• Setting up the development environment; Vivado + Vitis
• Configuration of the ZCU102 board for BGI application

Discussion with BI-DD on the use of SoC in BI: https://indico.cern.ch/event/1041826/

• Commonality with the BPM project where they will use the RFSoC
• Attempt to use the same TCP protocol between Zynq processor and FEC over 1G Ethernet