ELEC44

Tuesday Jun 1, 2010, 2:00 PM → 4:00 PM Europe/Zurich

513/1-027 (CERN)

Stefan Haas (CERN)

ELEC44 (01 Jun 2010)
Chaired by: Haas, Stefan

==================
Welcome
==================

ELEC 44

Present:  P. Baehler, J. Evans, Ph. Farthouat, S. Haas, W. Hofle, E. Jensen, A. Kluge, H. Meinhard, D. Nisbet,  E. van der Bij

Apologies for absence:  R. Denz.

E. van der Bij suggested that due to recent departmental changes, it might be useful to renew the ELEC committee composition.  S. Haas responded that recent changes had been reflected in new members.

P. Farthouat asked where CERN was in respect to verification training.  J.Evans said that this was being discussed with HR.

There were no other comments and the minutes for ELEC43 were approved.

==================
News from IT-PES
==================

Due to restructuration in IT, the EDA design support team is now part of the PES group led by Helge Meinhard.
He reported on the new group structure explaining that the main changes being made was the re-deployment of the database resources within the department.  He underlined that there would be no immediate changes in engineering support apparent to ELEC and the user committee. 
However, a new post had been opened  and this would hopefully lead to strengthening of the IT EDA support effort.  Originally announced  as a career path D vacancy, the post was re-advertised at CP E.
The announcement was received very positively by ELEC.

==================
Budget status. Plans for future investment.
==================

S. Haas asked if the 2011 budget situation was known.  IT members reported that it was too early to know the final allocated budget.

There had been a user request made to purchase a new USB 3 IP core.  ELEC noted that this was rather expensive and with no immediate widespread use.  It was asked that S. Haas investigate further to clarify the the urgency of the requirement.

E. Jensen then presented a request to acquire more HFSS field-solver licences. HFSS has for many years been a key  tool for:
– Accelerating structure design
– RF components design
– Impedance calculation analyses

Due to upgrade studies for different projects and accelerators (LHC luminosity upgrade, injectors upgrade, SPL,  ESS,  HIE‐Isolde,  PS2, CLIC, ...), there has been an increasing demand for licences.  E. Jensen then made a proposal where BE would purchase additional licences but he asked if ELEC would be willing to absorb some of the increased maintenance cost.

After discussion, ELEC accepted the validity of the request and asked that it be forwarded to IT. 

==================
Update on Cadence contract
==================

J. Evans reported that the Cadence contract update had been agreed and a new three year lease will start in July 2010.  All the present functionality will be kept available but there will also be a licence for the Allegro FPGA System Planner product.  This allows users to create an initial placement-aware pin assignment for one or more FPGAs.  It also allows PCB designers to later optimise pin assignments during final routing of signals on the PCB. 


==================
Status report on legacy software availablility
==================

P. Baehler presented the latest CERN Windows roadmap.  He also demonstrated  how CERN tools could be run on a W7 machine, with past and present versions available either directly or in a compatibility mode.
S. Haas said that the users should be presented with a recommendation on whether to update to Windows 7 or not as many tools were still not officially supported by the vendors.  It was proposed that ELEC could make a request to extend IT XP support if absolutely necessary.

J. Evans raised the issue of running FPGA-vendor supplied third-party tools.  Many vendors would supply OEM versions of software e.g. Synplify, Precision that would run only with a particular FPGA tool version and with the vendors’ devices.  It was almost impossible to guarantee that these legacy versions could be run in the future as the required licences often were no longer delivered by the FPGA vendors.  He suggested that only fully supported tool versions be used so as to try and avoid future difficulties.

==================
Report from EUG
==================

A. Kluge presented a resume of EUG25.

- The issue of legacy-device support remains important to the users.
- There is increasing interest in the field of verification and design language options to Verilog and VHDL.
- Users were satisfied with the Linux implementation of the Cadence tools
- A request had been made to investigate the possibility of acquiring an Altera triple-speed Ethernet IP core (NOTE: subsequently purchased - JE).
==================
AOB
==================

S.  Haas broached the subject of future CERN training topics.  There was a growing interest in verification at CERN and the last Friday afternoon for the coming TWEPP conference would be dedicated to the subject.  This was a follow-up to a successful 1 hour introductory session given at CERN as part of a VHDL training course given by Doulos. 
SystemVerilog was also seen as another possibility for use at CERN.  E. van der Bij expressed concern that this could lead to a division of support effort and a dilution in specialized knowledge.

It was mentioned that there was already quite extensive Veriliog expertise at CERN, particularly iin the sections involved with ASICs design.  SystemVerilog would be a natural extension of this knowledge and would help introduce verification techniques in a rather easy way.  This point was counteracted with the remark that CHDL2008 also includes many new verification constructs.

G. Agnileri is actively investigation the possible usefulness of SystemVerilog to CERN.

The date for the next meeting was nominally set to be the beginning of October.

2:00 PM → 2:05 PM Welcome

ELEC 44

Present:  P. Baehler, J. Evans, Ph. Farthouat, S. Haas, W. Hofle, E. Jensen, A. Kluge, H. Meinhard, D. Nisbet,  E. van der Bij

Apologies for absence:  R. Denz.

E. van der Bij suggested that due to recent departmental changes, it might be useful to renew the ELEC committee composition.  S. Haas responded that recent changes had been reflected in new members.

P. Farthouat asked where CERN was in respect to verification training.  J.Evans said that this was being discussed with HR.

There were no other comments and the minutes for ELEC43 were approved.
 

2:05 PM → 2:25 PM News from IT-PES

Due to restructuration in IT, the EDA design support team is now part of the PES group led by Helge Meinhard.
He reported on the new group structure explaining that the main changes being made was the re-deployment of the database resources within the department.  He underlined that there would be no immediate changes in engineering support apparent to ELEC and the user committee. 
However, a new post had been opened  and this would hopefully lead to strengthening of the IT EDA support effort.  Originally announced  as a career path D vacancy, the post was re-advertised at CP E.
The announcement was received very positively by ELEC.

2:25 PM → 2:50 PM Budget status. Plans for future investment.

Speaker: Dr Erk Jensen (CERN)

Slides EJ_HFSS_ELEC.pdf EJ_Memo_budget_for_simulation_tools.pdf

S. Haas asked if the 2011 budget situation was known.  IT members reported that it was too early to know the final allocated budget.

There had been a user request made to purchase a new USB 3 IP core.  ELEC noted that this was rather expensive and with no immediate widespread use.  It was asked that S. Haas investigate further to clarify the the urgency of the requirement.

E. Jensen then presented a request to acquire more HFSS field-solver licences. HFSS has for many years been a key  tool for:
– Accelerating structure design
– RF components design
– Impedance calculation analyses

Due to upgrade studies for different projects and accelerators (LHC luminosity upgrade, injectors upgrade, SPL,  ESS,  HIE‐Isolde,  PS2, CLIC, ...), there has been an increasing demand for licences.  E. Jensen then made a proposal where BE would purchase additional licences but he asked if ELEC would be willing to absorb some of the increased maintenance cost.

After discussion, ELEC accepted the validity of the request and asked that it be forwarded to IT. 
 

 

2:50 PM → 2:55 PM Update on Cadence contract

Speaker: John Evans (CERN)

J. Evans reported that the Cadence contract update had been agreed and a new three year lease will start in July 2010.  All the present functionality will be kept available but there will also be a licence for the Allegro FPGA System Planner product.  This allows users to create an initial placement-aware pin assignment for one or more FPGAs.  It also allows PCB designers to later optimise pin assignments during final routing of signals on the PCB. 

2:55 PM → 3:20 PM Status report on legacy software availablility

Speaker: Pierre Baehler (CERN)

Slides PB_ELEC44.pdf

P. Baehler presented the latest CERN Windows roadmap.  He also demonstrated  how CERN tools could be run on a W7 machine, with past and present versions available either directly or in a compatibility mode.
S. Haas said that the users should be presented with a recommendation on whether to update to Windows 7 or not as many tools were still not officially supported by the vendors.  It was proposed that ELEC could make a request to extend IT XP support if absolutely necessary.

J. Evans raised the issue of running FPGA-vendor supplied third-party tools.  Many vendors would supply OEM versions of software e.g. Synplify, Precision that would run only with a particular FPGA tool version and with the vendors’ devices.  It was almost impossible to guarantee that these legacy versions could be run in the future as the required licences often were no longer delivered by the FPGA vendors.  He suggested that only fully supported tool versions be used so as to try and avoid future difficulties.

3:20 PM → 3:40 PM Report from EUG

Speaker: Alex Kluge (CERN)

A. Kluge presented a resume of EUG25.

- The issue of legacy-device support remains important to the users.
- There is increasing interest in the field of verification and design language options to Verilog and VHDL.
- Users were satisfied with the Linux implementation of the Cadence tools
- A request had been made to investigate the possibility of acquiring an Altera triple-speed Ethernet IP core (NOTE: subsequently purchased - JE).

3:40 PM → 4:00 PM AOB

S.  Haas broached the subject of future CERN training topics.  There was a growing interest in verification at CERN and the last Friday afternoon for the coming TWEPP conference would be dedicated to the subject.  This was a follow-up to a successful 1 hour introductory session given at CERN as part of a VHDL training course given by Doulos. 
SystemVerilog was also seen as another possibility for use at CERN.  E. van der Bij expressed concern that this could lead to a division of support effort and a dilution in specialized knowledge.

It was mentioned that there was already quite extensive Veriliog expertise at CERN, particularly iin the sections involved with ASICs design.  SystemVerilog would be a natural extension of this knowledge and would help introduce verification techniques in a rather easy way.  This point was counteracted with the remark that CHDL2008 also includes many new verification constructs.

G. Agnileri is actively investigation the possible usefulness of SystemVerilog to CERN.

The date for the next meeting was nominally set to be the beginning of October.