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13:30
FELIX for ATLAS Run 4 Readout: Based on a Xilinx Versal Prime ACAP Device
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Nayib Boukadida
(Nikhef National institute for subatomic physics (NL))
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14:00
The Use of Xilinx Versal for the ATLAS Global Trigger
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David Sankey
(Science and Technology Facilities Council STFC (GB))
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14:30
Split Boot v2 - Simple and Reliable Network-Based Booting for Serenity-S1 and other Boards with ZynqMPs Devices
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Marvin Fuchs
(KIT - Karlsruhe Institute of Technology (DE))
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15:00
SoC Infrastructure for the ATLAS Phase-II Level-0 Central Trigger
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Ralf Spiwoks
(CERN)
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15:50
CMS DAQ System Design with Zynq MPSoC for Phase-2
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Petr Zejdl
(CERN)
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16:20
The CMS Barrel Muon Trigger Layer-1 Processor
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Ioannis Bestintzanos
(University of Ioannina (GR))
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16:50
Xilinx Versal ACAP/SoC for Real-Time or Quasi-Real Time Data Processing
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Benjamin John Rosser
(University of Chicago (US))
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17:20
HyperFPGA: an Experimental Testbed for Future Heterogeneous Cluster Architectures
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Werner Oswaldo Florian Samayoa
(Universita e INFN Trieste (IT))
