BE Seminar > Giulio

Wednesday 17 May 2023, 09:00 → 10:00 Europe/Zurich

13/3-005 (CERN)

09:00 → 09:50 Scalable booting and host configuration for Systems-on-Chips in the ATLAS Level 1 Central Trigger

Systems-on-Chip (SoCs) are devices where a processor is paired with an FPGA. This combination allows one to run triggers at very high speed in silicon, while retaining the flexibility of a standard Linux computer for configuration, control and monitoring tasks. The ATLAS Level 1 Central Trigger system uses SoCs on a number of its modules: on the Muon to Central Trigger Processor Interface (MUCTPI) already commissioned in the experiment, but also on the Local Trigger Interface (LTI), and on the Central Trigger processor (CTP) for the Phase-2 upgrades. A total of 10 modules and prototypes are currently being used in the experiment and in the labs, and in Phase-2 up to 50 modules may be deployed in the experiment. In addition, other sub-systems in ATLAS and CMS also foresee to use SoCs in their upgrades. Thus, all steps of the lifecycle, from software compilation, to booting and host configuration must be designed to work efficiently with a large number of SoCs deployed on a variety of modules.
This seminar will present some techniques developed in the ATLAS L1CT group to address these issues. We will review our experience with these techniques and discuss how they are being contributed to the wider SoC community at CERN.

Speaker: Giulio Muscarello (Politecnico di Torino (IT))

SoC for for Phase 2 L0CT.pdf

SoC for Phase 2 L0CT.pptx

09:50 → 10:00 Questions and Answers