Neural networks have been widely utilized in neuroscience experiments. A specific brain signal, sleep spindle, is believed to associate with learning and memory. To reveal the underlying mechanism behind this association, a complex neural network model named Multi-block RNN Autoencoders (MREA) will be used. MRAE has shown a satisfactory performance in modeling the brain signals and the possibility to uncover the unclear mechanism of how sleep spindles contribute to learning and memory. In order to realize the real-time system for analyzing sleep spindles, the Field Programmable Gate Array (FPGA) was used to accelerate the model. Because of the substantial size of the MREA, we initially deployed its baseline model, Latent Factor Analysis via Dynamical Systems (LFADS), onto FPGA. The model was translated to hardware languages by HLS4ML (High-Level Synthesis for Machine Learning), which is a framework that converts the traditional machine learning models to the deployment-ready HLS models. We deployed the LFADS onto Xilinx U55C by modifying its architecture and implementing the HLS4ML package. The modification of the LFADS architecture, implementation of the HLS4ML, and the on-board performance are discussed in this thesis.