Speaker
Prof.
Toshinobu Miyoshi
(Institute of Particle and Nuclear Studies, High Energy Accelerator Research Organization (KEK))
Description
We are developing monolithic pixel detectors
with a 0.2 um Fully-Depleted (FD) silicon-on-insulator
(SOI) CMOS technology. The substrate layer
is high-resistivity silicon, and works
as a radiation sensor having p-n junctions.
The SOI layer is 40-nm silicon, where
readout electronics is implemented.
There is a buried oxide layer between these silicon layers.
This structure is ideal for a monolithic pixel detector.
We developed p-in-n and n-in-p SOI pixel sensors
with Czochralski (CZ) or Float Zone (FZ) silicon substrate.
We operated the 500-um-thick, FZ SOI pixel detectors
under full depletion voltage.
In this presentation we show resent test results
of the SOI pixel detectors
about the characteristics
such as sensitivity, spatial resolution,
energy resolution and radiation tolerance.
Author
Prof.
Toshinobu Miyoshi
(Institute of Particle and Nuclear Studies, High Energy Accelerator Research Organization (KEK))
