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RD50 CMOS Sensor Meeting

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RD50 CMOS Sensor Meeting
Zoom Meeting ID
94676963354
Host
Eva Vilella Figueras
Passcode
46926294
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    • 1
      RD50-MPW4 - News
      • RD50-MPW4 samples arrived at CERN right before the Christmas break (topside biased samples only), samples arrived to Liverpool yesterday; samples will be distributed to interested institutes
      • RD50-MPW4 backside biased samples: dicing planned for 15.01.2024
      • PCB fabrication and distribution update (for measuring active matrix with Caribou)?
      • Design of small PCB for I-V & eTCT measurements (for measuring test structures only)?
      Speakers: Eva Vilella Figueras (University of Liverpool (GB)), Dr Ricardo Marco Hernandez (CERN), Ricardo Marco Hernandez (Instituto de Fisica Corpuscular (ES)), Samuel Powell (University of Liverpool (GB))
      Chip pictures
    • 2
      RD50-MPW3
      • Lab measurements before and after irradiation
      Speakers: Benjamin Wade (University of Liverpool (GB)), Bernhard Pilsl (Austrian Academy of Sciences (AT)), Chenfan Zhang (University of Liverpool (GB)), Chenfan Zhang (University of Liverpool), Christian Irmler (Austrian Academy of Sciences (AT)), Douwe Nobels, Helmut Steininger (Austrian Academy of Sciences (AT)), Patrick Sieberer (Austrian Academy of Sciences (AT)), Samuel Powell (University of Liverpool (GB)), Thijs Niemeijer (Nikhef), Uwe Kraemer
      tdac_eval.pdf
    • 3
      Question from Athens University colleagues

      Message received:
      I am professor at the Aerospace Science and Technology Department of the National and Kapodistrian University of Athens. Our group develops HVCMOS sensors for monitoring the radiation field in space.
      The reason I am contacting you is the following:
      We use the same technology as your group (LF 150nm) in the chips we have developed (see the attached manuscript submitted to the TWEPP 2023 proceedings),amongst other issues, we observe an ohmic connection between the analog Vdd and the digital Vdd. As this should not happen we have a theory that perhaps this connection originates from the insufficient distance (5 μm) between a DNWELL biased at Vdd analog and a DNWELL biased at Vdd digital. These DNWELLs reside at the bottom area of the chip outside the pixel array and house analog circuitry and the embedded controller respectively. The situation refers to the "low gain" chip (see the attached manuscript), while the "high gain" one is not yet received.

      DNW_spacing.pdf
    • 4
      AOB
      • Beam Telescopes and Test Beams Workshop, deadline for submitting abstracts is 14.01.2024
      BTTB WS
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