Tutorial on SoC Co-Simulation

• Hamza Boukabache (CERN)
• Clyde Laforge (CERN)

Room: 40/S2-C01 - Salle Marie Sklodowska-Curie A comprehensive co-simulation framework for System-on-Chip (SoC) serves as an invaluable tool for testing and verifying heterogeneous designs that incorporate complex HDL (Hardware Description Language) and operating systems under real-world conditions. This approach facilitates an in-depth exploration of the interactions between HDL, software, and real-world scenarios in ways that are unattainable through other means, while also streamlining the debugging process on actual hardware platforms. In this presentation, we will showcase the implementation of co-simulation within the CROME system, employing a combination of a mixed-language RTL (Register Transfer Level) simulator, libsystemctlm, and QEMU. We will elucidate how these components integrate, highlight the compromises involved, and provide guidance on developing a similar co-simulation environment for your projects.

Update on SoC Activities in the CERN AT Sector

• Irene Degl'Innocenti (CERN)

Room: 40/S2-C01 - Salle Marie Sklodowska-Curie