CHIPS - ETROC Review

Tuesday 27 Feb 2024, 17:00 → 19:00 Europe/Zurich

14/5-022 (CERN)

MTD_ETL_Report_Feb6.pdf

17:00 → 17:20 ETROC3 Discussion

1) General description of the architecture. Prepare detailed block diagram where we can understand the design architecture and identify the blocks that require modifications.

2) Description of the implementation methodology. Analog-On-Top or digital-on-top? Fullchip level STA? how is this verified with the testbench? Are there functional Verilog models of the "analog" macro blocks (PLLs, phase shifters,...) ?

3) Clock architecture. Clock domains and how are implemented

4) Reset architecture. Synchronous vs Asynchronous reset.

5) Is the required support to be done on the digital side only?

6) It seems that the required support is mainly focused on the improvement of the SEE robustness. Provide full detail of how the actual design is triplicated. Do you have experience using TMRG tool?

7) Description of the current functional verification environment available. Is it UVM based? Does exist an SEE injection strategy?

8) Design repository structure (Git, Cliosoft,...). Otherwise, where/how are the RTL, UVM and PNR SCRIPTS stored?

Speaker: Xavi Llopart Cudie (CERN)

17:20 → 17:40 ETROC2

Presentation by Datao Gong

The SEE protection considertion and verification in ETROC2.pdf

The SEE protection considertion and verification in ETROC2.pptx