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BI/TB: BLM ASIC
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BI/TB: BLM ASIC
The BLM ASIC V3 is rad-tol up to 1MGy due the technology capabilities but it is not due to the needs of the project.
It was pointed out that when 5mA is passed and the protection diode kicks in, it is important that the current measured stay up to be able to interlock and protect. Ewald said that in any case with the limits set as they are now the system requests a dump before getting to 5mA.
Changing the ADC would improve the performance, but this would be a major effort and imply a change of technology.
Simulations would help reducing the number of iterations (ASICS production’s cycle) but there is a large uncertainty, especially in this technolog.
The production should be in the next 5 years or there is the risk of not having access to the process anymore.
Moving to 65nm is major effort, and some considerations needs to be addressed when it comes to leakage, tho using thick oxide structures should solve/mitigate the issue.
The current design has the redundant links arriving to the same FPGA, where the redundancy finishes.It might be possible to increase the redundancy splitting the processing in 2 VFC and ideally crates.
This is to be considered for the LHC, but for the SPS there is not tome and just a crate per point.
The BLM ASIC V3 meets the required performance/specifications, V4 would bring some improvements and would address the fast losses at injection. For those scenarios it should also be investigated the possibility to use different geometry ionisation chambers.
For the buffer to interface to the LpGBT the plan is:
- check if an ASIC from ESE is available
- if no ASIC from ESE is available, check if there is a COT in the RADWG qualified
- if none of the above option is viable, qualify a COT
The production of the 200 BLM ASIC V3 should be advanced to 2024 to anticipate the work in the SPS and avoid that it might collide with the LHC peak work in 2027
Next production of BLM ASICS for the additional 5k required, needs to be a full one (not MPW) and this means 35k ASICs produced
Increasing the maximum input current to 100mA might not be possible even in 65nm:
- going to 64nm there is a factor 2 and not 2 order of magnitude
- 100mA is the melting limit for a standard bump bonding
The SPS BLM system will be erquipped with V3 and the design is probably not the same that will be deployed for the LHC
For the MPW it might be possible to ask to join the May run.
There is otherwise possibly another run (not yet programmed) for September or October. (did we not say that next production would need to be a full production run?)
The issue leading to the potential need of a V4 is the high losses happening at injection, but this is mostly to be addressed on the board. Moreover this is for a small subset of deployed systems, and would work if the ionisation chamber is not saturating. It might be worth going for a smaller detector: a study should be started. A more global approach should be envisaged. <= Action on BLM section
Side note on AccPy not being supported in the FECs, and updates in AccPy breaks the EDGEGUI <= action on T and SL
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