Speaker
Description
CERN's Large Hadron Collider (LHC) is undergoing a major upgrade that will increase its luminosity by a factor of 10. The new High-Luminosity LHC (HL-LHC) will advance the frontier of knowledge in particle physics, but it also poses an unprecedented challenge in the design of the electronics for its particle detectors. The inner layers of the new detectors will have to withstand levels of total ionizing dose (TID) up to 1 Grad (10 MGy) and fluences in the order of 10¹⁶ neq/cm² after 10 years of operation. This talk illustrates the main effects caused by these extreme radiation levels on the commercial CMOS technologies used in the design of application-specific integrated circuits (ASICs) for particle detectors, showing the consequences of these effects both at transistor level and on complex chips. Particular attention will be given to the mechanisms of charge transport and trapping in MOS transistor oxides, as well as the design strategies employed to mitigate the impact of single-event effects (SEEs).
