Caribou Developers Meeting

Tuesday 28 May 2024, 16:00 → 17:30 Europe/Zurich

Younes Otarid (CERN)

16:00 → 16:10 General News

Speaker: Younes Otarid (CERN)

Younes:

Caribou Developers meetings will from now on be held on Tuesdays, bi-weekly. But still need to determine odd or even weeks to always keep the same pattern.

 

16:10 → 16:35 Hardware

Speakers: Eric Buschmann (Brookhaven National Laboratory (US)), Shaochun Tang (Brookhaven National Laboratory (US)), Tomas Vanat (Deutsches Elektronen-Synchrotron (DE)), Younes Otarid (CERN)

Tomas + Younes:

• Tomas contacted Safiral to clarify details of the service:
  • Assembly + Testing 
    • PCB electrical tests and impedance matching control
      • Included by default --> Requested
    • Optical inspection (AOI) of the soldered components
      • Included by default --> Requested
    • X-ray screening 
      • Possible with extra costs --> Discarded
    • Functional tests
      • Possible but would lead to extra costs --> Discarded
    • IPC class 2 for PCB assembly

 

• • Pricing and order
    • Price scaling to 31 boards is linear, which means 
      • 776€ / board (includes PCB, assembly, components and services)
    • Components price might change as the current quotation is one month old. New invoice should be sent to the purchasing office
    • Request is ready with all 3 quotations and comments on chosen supplier.
      • https://edh.cern.ch/Document/SupplyChain/DAI/10293018
      • Will be submitted by the end of the day
    • Request from Safiral for pre-payment from CERN could lead to additional delays in production.
      • Will get in touch with the purchasing office to clarify situation

 

Eric:

• Internal discussion at BNL about Caribou v2.0.
• Conclusion was, while Max did a lot of work, the design is incomplete with very floaty design choices.
• Currently reiterating on requirements and design ideas that are still to be defined
• Will prepare a presentation for the coming weeks that shall put all Developers on the same page about the v2.0 design and plans

16:35 → 17:00 Firmware

Speakers: Eric Buschmann (Brookhaven National Laboratory (US)), Tomas Vanat (Deutsches Elektronen-Synchrotron (DE)), Younes Otarid (CERN)

Younes:

• Improved the architecture to support multiple boards
  • Initially architecture was separated into two hierarchical structures, one for each board. This was done because of an issue with locked IPs and imcompatibility between the configured target device and the constraints files included in the synthesis flow. And the correct architecture was picked by defining the top module corresponding to the chosen board.
  • Disadvantage is that it leads to some code duplication
  • Solution was:
    • merge the two structures into a single top file
    • use generate statements to instantiate board PS IPs
    • exclude the PS IPs of the non-targeted boards from the synthesis workflow.
  • This way, the Boreal firmware relies on a single hierarchical structure, and all the needed configuration is handled by the BorealManager 

 

• Working on moving the existing common blocks (Patter Generator, Pulse Generator, Syncers, ...)

 

• Included linting into BorealManager

 

17:00 → 17:25 Software - OS

Speakers: Eric Buschmann (Brookhaven National Laboratory (US)), Mathieu Benoit (Oak Ridge National Laboratory (ORNL)), Simon Spannagel (Deutsches Elektronen-Synchrotron (DE)), Younes Otarid (CERN)

Younes:

• Installed PetaLinux build tools
• Started looking at the build workflow, working on understanding the needed configurations, and how to include Peary as a layer
• Objectives are:
  • Understand the complete build workflow 
  • Build an image for one ZCU102 (MPSoC) board
  • Implement a streamlined and automatized build workflow
  • Reiterate for the ZC706 (Zynq) board to close on support of all boards

 

17:25 → 17:30 AOB